<!DOCTYPE html><html><head><title>x86 Assembly Documentation</title></head>
<body><h1>x86 Assembly Documentation</h1><p>Html pages generated with <a href="https://github.com/HJLebbink/x86doc">x86doc</a></p>
<table>
<tr><td><a href="./html/AAA.html">AAA</a></td><td>ASCII Adjust After Addition</td><td></td></tr>
<tr><td><a href="./html/AAD.html">AAD</a></td><td>ASCII Adjust AX Before Division</td><td></td></tr>
<tr><td><a href="./html/AAM.html">AAM</a></td><td>ASCII Adjust AX After Multiply</td><td></td></tr>
<tr><td><a href="./html/AAS.html">AAS</a></td><td>ASCII Adjust AL After Subtraction</td><td></td></tr>
<tr><td><a href="./html/ADC.html">ADC</a></td><td>Add with Carry</td><td></td></tr>
<tr><td><a href="./html/ADCX.html">ADCX</a></td><td>Unsigned Integer Addition of Two Operands with Carry Flag</td><td>ADX</td></tr>
<tr><td><a href="./html/ADD.html">ADD</a></td><td>Add</td><td></td></tr>
<tr><td><a href="./html/ADDPD.html">ADDPD</a></td><td>Add Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ADDPS.html">ADDPS</a></td><td>Add Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/ADDSD.html">ADDSD</a></td><td>Add Scalar Double-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/ADDSS.html">ADDSS</a></td><td>Add Scalar Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/ADDSUBPD.html">ADDSUBPD</a></td><td>Packed Double-FP Add/Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/ADDSUBPS.html">ADDSUBPS</a></td><td>Packed Single-FP Add/Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/ADOX.html">ADOX</a></td><td>Unsigned Integer Addition of Two Operands with Overflow Flag</td><td>ADX</td></tr>
<tr><td><a href="./html/AESDEC.html">AESDEC</a></td><td>Perform One Round of an AES Decryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESDECLAST.html">AESDECLAST</a></td><td>Perform Last Round of an AES Decryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESENC.html">AESENC</a></td><td>Perform One Round of an AES Encryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESENCLAST.html">AESENCLAST</a></td><td>Perform Last Round of an AES Encryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESIMC.html">AESIMC</a></td><td>Perform the AES InvMixColumn Transformation</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESKEYGENASSIST.html">AESKEYGENASSIST</a></td><td>AES Round Key Generation Assist</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AND.html">AND</a></td><td>Logical AND</td><td></td></tr>
<tr><td><a href="./html/ANDN.html">ANDN</a></td><td>Logical AND NOT</td><td>BMI1</td></tr>
<tr><td><a href="./html/ANDNPD.html">ANDNPD</a></td><td>Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ANDNPS.html">ANDNPS</a></td><td>Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/ANDPD.html">ANDPD</a></td><td>Bitwise Logical AND of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ANDPS.html">ANDPS</a></td><td>Bitwise Logical AND of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/ARPL.html">ARPL</a></td><td>Adjust RPL Field of Segment Selector</td><td></td></tr>
<tr><td><a href="./html/BEXTR.html">BEXTR</a></td><td>Bit Field Extract</td><td></td></tr>
<tr><td><a href="./html/BLENDPD.html">BLENDPD</a></td><td>Blend Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/BLENDPS.html">BLENDPS</a></td><td>Blend Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/BLENDVPD.html">BLENDVPD</a></td><td>Variable Blend Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/BLENDVPS.html">BLENDVPS</a></td><td>Variable Blend Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/BLSI.html">BLSI</a></td><td>Extract Lowest Set Isolated Bit</td><td>BMI1</td></tr>
<tr><td><a href="./html/BLSMSK.html">BLSMSK</a></td><td>Get Mask Up to Lowest Set Bit</td><td>BMI1</td></tr>
<tr><td><a href="./html/BLSR.html">BLSR</a></td><td>Reset Lowest Set Bit</td><td>BMI1</td></tr>
<tr><td><a href="./html/BNDCL.html">BNDCL</a></td><td>Check Lower Bound</td><td>MPX</td></tr>
<tr><td><a href="./html/BNDCU_BNDCN.html">BNDCN</a></td><td>Check Upper Bound</td><td>MPX</td></tr>
<tr><td><a href="./html/BNDCU_BNDCN.html">BNDCU</a></td><td>Check Upper Bound</td><td>MPX</td></tr>
<tr><td><a href="./html/BNDLDX.html">BNDLDX</a></td><td>Load Extended Bounds Using Address Translation</td><td>MPX</td></tr>
<tr><td><a href="./html/BNDMK.html">BNDMK</a></td><td>Make Bounds</td><td>MPX</td></tr>
<tr><td><a href="./html/BNDMOV.html">BNDMOV</a></td><td>Move Bounds</td><td>MPX</td></tr>
<tr><td><a href="./html/BNDSTX.html">BNDSTX</a></td><td>Store Extended Bounds Using Address Translation</td><td>MPX</td></tr>
<tr><td><a href="./html/BOUND.html">BOUND</a></td><td>Check Array Index Against Bounds</td><td></td></tr>
<tr><td><a href="./html/BSF.html">BSF</a></td><td>Bit Scan Forward</td><td></td></tr>
<tr><td><a href="./html/BSR.html">BSR</a></td><td>Bit Scan Reverse</td><td></td></tr>
<tr><td><a href="./html/BSWAP.html">BSWAP</a></td><td>Byte Swap</td><td></td></tr>
<tr><td><a href="./html/BT.html">BT</a></td><td>Bit Test</td><td></td></tr>
<tr><td><a href="./html/BTC.html">BTC</a></td><td>Bit Test and Complement</td><td></td></tr>
<tr><td><a href="./html/BTR.html">BTR</a></td><td>Bit Test and Reset</td><td></td></tr>
<tr><td><a href="./html/BTS.html">BTS</a></td><td>Bit Test and Set</td><td></td></tr>
<tr><td><a href="./html/BZHI.html">BZHI</a></td><td>Zero High Bits Starting with Specified Bit Position</td><td></td></tr>
<tr><td><a href="./html/CALL.html">CALL</a></td><td>Call Procedure</td><td></td></tr>
<tr><td><a href="./html/CBW_CWDE_CDQE.html">CBW</a></td><td>Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword</td><td></td></tr>
<tr><td><a href="./html/CWD_CDQ_CQO.html">CDQ</a></td><td>Convert Word to Doubleword/Convert Doubleword to Quadword</td><td></td></tr>
<tr><td><a href="./html/CBW_CWDE_CDQE.html">CDQE</a></td><td>Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword</td><td></td></tr>
<tr><td><a href="./html/CLAC.html">CLAC</a></td><td>Clear AC Flag in EFLAGS Register</td><td></td></tr>
<tr><td><a href="./html/CLC.html">CLC</a></td><td>Clear Carry Flag</td><td></td></tr>
<tr><td><a href="./html/CLD.html">CLD</a></td><td>Clear Direction Flag</td><td></td></tr>
<tr><td><a href="./html/CLFLUSH.html">CLFLUSH</a></td><td>Flush Cache Line</td><td></td></tr>
<tr><td><a href="./html/CLFLUSHOPT.html">CLFLUSHOPT</a></td><td>Flush Cache Line Optimized</td><td></td></tr>
<tr><td><a href="./html/CLI.html">CLI</a></td><td>Clear Interrupt Flag</td><td></td></tr>
<tr><td><a href="./html/CLTS.html">CLTS</a></td><td>Clear Task-Switched Flag in CR0</td><td></td></tr>
<tr><td><a href="./html/CMC.html">CMC</a></td><td>Complement Carry Flag</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVA</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVAE</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVB</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVBE</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVC</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVE</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVG</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVGE</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVL</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVLE</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVNA</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVNAE</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMOVcc.html">CMOVNB</a></td><td>Conditional Move</td><td></td></tr>
<tr><td><a href="./html/CMP.html">CMP</a></td><td>Compare Two Operands</td><td></td></tr>
<tr><td><a href="./html/CMPPD.html">CMPPD</a></td><td>Compare Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CMPPS.html">CMPPS</a></td><td>Compare Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/CMPS_CMPSB_CMPSW_CMPSD_CMPSQ.html">CMPS</a></td><td>Compare String Operands</td><td></td></tr>
<tr><td><a href="./html/CMPS_CMPSB_CMPSW_CMPSD_CMPSQ.html">CMPSB</a></td><td>Compare String Operands</td><td></td></tr>
<tr><td><a href="./html/CMPS_CMPSB_CMPSW_CMPSD_CMPSQ.html">CMPSD</a></td><td>Compare String Operands</td><td></td></tr>
<tr><td><a href="./html/CMPS_CMPSB_CMPSW_CMPSD_CMPSQ.html">CMPSQ</a></td><td>Compare String Operands</td><td></td></tr>
<tr><td><a href="./html/CMPSS.html">CMPSS</a></td><td>Compare Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/CMPS_CMPSB_CMPSW_CMPSD_CMPSQ.html">CMPSW</a></td><td>Compare String Operands</td><td></td></tr>
<tr><td><a href="./html/CMPXCHG.html">CMPXCHG</a></td><td>Compare and Exchange</td><td></td></tr>
<tr><td><a href="./html/CMPXCHG8B_CMPXCHG16B.html">CMPXCHG16B</a></td><td>Compare and Exchange Bytes</td><td></td></tr>
<tr><td><a href="./html/CMPXCHG8B_CMPXCHG16B.html">CMPXCHG8B</a></td><td>Compare and Exchange Bytes</td><td></td></tr>
<tr><td><a href="./html/COMISD.html">COMISD</a></td><td>Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/COMISS.html">COMISS</a></td><td>Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/CPUID.html">CPUID</a></td><td>CPU Identification</td><td></td></tr>
<tr><td><a href="./html/CWD_CDQ_CQO.html">CQO</a></td><td>Convert Word to Doubleword/Convert Doubleword to Quadword</td><td></td></tr>
<tr><td><a href="./html/CRC32.html">CRC32</a></td><td>Accumulate CRC32 Value</td><td></td></tr>
<tr><td><a href="./html/CVTDQ2PD.html">CVTDQ2PD</a></td><td>Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTDQ2PS.html">CVTDQ2PS</a></td><td>Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPD2DQ.html">CVTPD2DQ</a></td><td>Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPD2PI.html">CVTPD2PI</a></td><td>Convert Packed Double-Precision FP Values to Packed Dword Integers</td><td></td></tr>
<tr><td><a href="./html/CVTPD2PS.html">CVTPD2PS</a></td><td>Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPI2PD.html">CVTPI2PD</a></td><td>Convert Packed Dword Integers to Packed Double-Precision FP Values</td><td></td></tr>
<tr><td><a href="./html/CVTPI2PS.html">CVTPI2PS</a></td><td>Convert Packed Dword Integers to Packed Single-Precision FP Values</td><td></td></tr>
<tr><td><a href="./html/CVTPS2DQ.html">CVTPS2DQ</a></td><td>Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPS2PD.html">CVTPS2PD</a></td><td>Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPS2PI.html">CVTPS2PI</a></td><td>Convert Packed Single-Precision FP Values to Packed Dword Integers</td><td></td></tr>
<tr><td><a href="./html/CVTSD2SI.html">CVTSD2SI</a></td><td>Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTSD2SS.html">CVTSD2SS</a></td><td>Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTSI2SD.html">CVTSI2SD</a></td><td>Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTSI2SS.html">CVTSI2SS</a></td><td>Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/CVTSS2SD.html">CVTSS2SD</a></td><td>Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTSS2SI.html">CVTSS2SI</a></td><td>Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/CVTTPD2DQ.html">CVTTPD2DQ</a></td><td>Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTTPD2PI.html">CVTTPD2PI</a></td><td>Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers</td><td></td></tr>
<tr><td><a href="./html/CVTTPS2DQ.html">CVTTPS2DQ</a></td><td>Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTTPS2PI.html">CVTTPS2PI</a></td><td>Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers</td><td></td></tr>
<tr><td><a href="./html/CVTTSD2SI.html">CVTTSD2SI</a></td><td>Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTTSS2SI.html">CVTTSS2SI</a></td><td>Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/CWD_CDQ_CQO.html">CWD</a></td><td>Convert Word to Doubleword/Convert Doubleword to Quadword</td><td></td></tr>
<tr><td><a href="./html/CBW_CWDE_CDQE.html">CWDE</a></td><td>Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword</td><td></td></tr>
<tr><td><a href="./html/DAA.html">DAA</a></td><td>Decimal Adjust AL after Addition</td><td></td></tr>
<tr><td><a href="./html/DAS.html">DAS</a></td><td>Decimal Adjust AL after Subtraction</td><td></td></tr>
<tr><td><a href="./html/DEC.html">DEC</a></td><td>Decrement by 1</td><td></td></tr>
<tr><td><a href="./html/DIV.html">DIV</a></td><td>Unsigned Divide</td><td></td></tr>
<tr><td><a href="./html/DIVPD.html">DIVPD</a></td><td>Divide Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/DIVPS.html">DIVPS</a></td><td>Divide Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/DIVSD.html">DIVSD</a></td><td>Divide Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/DIVSS.html">DIVSS</a></td><td>Divide Scalar Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/DPPD.html">DPPD</a></td><td>Dot Product of Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/DPPS.html">DPPS</a></td><td>Dot Product of Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/EMMS.html">EMMS</a></td><td>Empty MMX Technology State</td><td></td></tr>
<tr><td><a href="./html/ENTER.html">ENTER</a></td><td>Make Stack Frame for Procedure Parameters</td><td></td></tr>
<tr><td><a href="./html/EXTRACTPS.html">EXTRACTPS</a></td><td>Extract Packed Floating-Point Values</td><td>AVX, AVX512F, SSE4_1</td></tr>
<tr><td><a href="./html/F2XM1.html">F2XM1</a></td><td>Compute 2x–1</td><td></td></tr>
<tr><td><a href="./html/FABS.html">FABS</a></td><td>Absolute Value</td><td></td></tr>
<tr><td><a href="./html/FADD_FADDP_FIADD.html">FADD</a></td><td>Add</td><td></td></tr>
<tr><td><a href="./html/FADD_FADDP_FIADD.html">FADDP</a></td><td>Add</td><td></td></tr>
<tr><td><a href="./html/FBLD.html">FBLD</a></td><td>Load Binary Coded Decimal</td><td></td></tr>
<tr><td><a href="./html/FBSTP.html">FBSTP</a></td><td>Store BCD Integer and Pop</td><td></td></tr>
<tr><td><a href="./html/FCHS.html">FCHS</a></td><td>Change Sign</td><td></td></tr>
<tr><td><a href="./html/FCLEX_FNCLEX.html">FCLEX</a></td><td>Clear Exceptions</td><td></td></tr>
<tr><td><a href="./html/FCMOVcc.html">FCMOVB</a></td><td>Floating-Point Conditional Move</td><td></td></tr>
<tr><td><a href="./html/FCMOVcc.html">FCMOVBE</a></td><td>Floating-Point Conditional Move</td><td></td></tr>
<tr><td><a href="./html/FCMOVcc.html">FCMOVE</a></td><td>Floating-Point Conditional Move</td><td></td></tr>
<tr><td><a href="./html/FCMOVcc.html">FCMOVNB</a></td><td>Floating-Point Conditional Move</td><td></td></tr>
<tr><td><a href="./html/FCMOVcc.html">FCMOVNBE</a></td><td>Floating-Point Conditional Move</td><td></td></tr>
<tr><td><a href="./html/FCMOVcc.html">FCMOVNE</a></td><td>Floating-Point Conditional Move</td><td></td></tr>
<tr><td><a href="./html/FCMOVcc.html">FCMOVU</a></td><td>Floating-Point Conditional Move</td><td></td></tr>
<tr><td><a href="./html/FCOM_FCOMP_FCOMPP.html">FCOM</a></td><td>Compare Floating Point Values</td><td></td></tr>
<tr><td><a href="./html/FCOMI_FCOMIP_FUCOMI_FUCOMIP.html">FCOMI</a></td><td>Compare Floating Point Values and Set EFLAGS</td><td></td></tr>
<tr><td><a href="./html/FCOMI_FCOMIP_FUCOMI_FUCOMIP.html">FCOMIP</a></td><td>Compare Floating Point Values and Set EFLAGS</td><td></td></tr>
<tr><td><a href="./html/FCOM_FCOMP_FCOMPP.html">FCOMP</a></td><td>Compare Floating Point Values</td><td></td></tr>
<tr><td><a href="./html/FCOM_FCOMP_FCOMPP.html">FCOMPP</a></td><td>Compare Floating Point Values</td><td></td></tr>
<tr><td><a href="./html/FCOS.html">FCOS</a></td><td>Cosine</td><td></td></tr>
<tr><td><a href="./html/FDECSTP.html">FDECSTP</a></td><td>Decrement Stack-Top Pointer</td><td></td></tr>
<tr><td><a href="./html/FDIV_FDIVP_FIDIV.html">FDIV</a></td><td>Divide</td><td></td></tr>
<tr><td><a href="./html/FDIV_FDIVP_FIDIV.html">FDIVP</a></td><td>Divide</td><td></td></tr>
<tr><td><a href="./html/FDIVR_FDIVRP_FIDIVR.html">FDIVR</a></td><td>Reverse Divide</td><td></td></tr>
<tr><td><a href="./html/FDIVR_FDIVRP_FIDIVR.html">FDIVRP</a></td><td>Reverse Divide</td><td></td></tr>
<tr><td><a href="./html/FFREE.html">FFREE</a></td><td>Free Floating-Point Register</td><td></td></tr>
<tr><td><a href="./html/FADD_FADDP_FIADD.html">FIADD</a></td><td>Add</td><td></td></tr>
<tr><td><a href="./html/FICOM_FICOMP.html">FICOM</a></td><td>Compare Integer</td><td></td></tr>
<tr><td><a href="./html/FICOM_FICOMP.html">FICOMP</a></td><td>Compare Integer</td><td></td></tr>
<tr><td><a href="./html/FDIV_FDIVP_FIDIV.html">FIDIV</a></td><td>Divide</td><td></td></tr>
<tr><td><a href="./html/FDIVR_FDIVRP_FIDIVR.html">FIDIVR</a></td><td>Reverse Divide</td><td></td></tr>
<tr><td><a href="./html/FILD.html">FILD</a></td><td>Load Integer</td><td></td></tr>
<tr><td><a href="./html/FMUL_FMULP_FIMUL.html">FIMUL</a></td><td>Multiply</td><td></td></tr>
<tr><td><a href="./html/FINCSTP.html">FINCSTP</a></td><td>Increment Stack-Top Pointer</td><td></td></tr>
<tr><td><a href="./html/FINIT_FNINIT.html">FINIT</a></td><td>Initialize Floating-Point Unit</td><td></td></tr>
<tr><td><a href="./html/FIST_FISTP.html">FIST</a></td><td>Store Integer</td><td></td></tr>
<tr><td><a href="./html/FIST_FISTP.html">FISTP</a></td><td>Store Integer</td><td></td></tr>
<tr><td><a href="./html/FISTTP.html">FISTTP</a></td><td>Store Integer with Truncation</td><td></td></tr>
<tr><td><a href="./html/FSUB_FSUBP_FISUB.html">FISUB</a></td><td>Subtract</td><td></td></tr>
<tr><td><a href="./html/FSUBR_FSUBRP_FISUBR.html">FISUBR</a></td><td>Reverse Subtract</td><td></td></tr>
<tr><td><a href="./html/FLD.html">FLD</a></td><td>Load Floating Point Value</td><td></td></tr>
<tr><td><a href="./html/FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html">FLD1</a></td><td>Load Constant</td><td></td></tr>
<tr><td><a href="./html/FLDCW.html">FLDCW</a></td><td>Load x87 FPU Control Word</td><td></td></tr>
<tr><td><a href="./html/FLDENV.html">FLDENV</a></td><td>Load x87 FPU Environment</td><td></td></tr>
<tr><td><a href="./html/FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html">FLDL2E</a></td><td>Load Constant</td><td></td></tr>
<tr><td><a href="./html/FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html">FLDL2T</a></td><td>Load Constant</td><td></td></tr>
<tr><td><a href="./html/FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html">FLDLG2</a></td><td>Load Constant</td><td></td></tr>
<tr><td><a href="./html/FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html">FLDLN2</a></td><td>Load Constant</td><td></td></tr>
<tr><td><a href="./html/FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html">FLDPI</a></td><td>Load Constant</td><td></td></tr>
<tr><td><a href="./html/FLD1_FLDL2T_FLDL2E_FLDPI_FLDLG2_FLDLN2_FLDZ.html">FLDZ</a></td><td>Load Constant</td><td></td></tr>
<tr><td><a href="./html/FMUL_FMULP_FIMUL.html">FMUL</a></td><td>Multiply</td><td></td></tr>
<tr><td><a href="./html/FMUL_FMULP_FIMUL.html">FMULP</a></td><td>Multiply</td><td></td></tr>
<tr><td><a href="./html/FCLEX_FNCLEX.html">FNCLEX</a></td><td>Clear Exceptions</td><td></td></tr>
<tr><td><a href="./html/FINIT_FNINIT.html">FNINIT</a></td><td>Initialize Floating-Point Unit</td><td></td></tr>
<tr><td><a href="./html/FNOP.html">FNOP</a></td><td>No Operation</td><td></td></tr>
<tr><td><a href="./html/FSAVE_FNSAVE.html">FNSAVE</a></td><td>Store x87 FPU State</td><td></td></tr>
<tr><td><a href="./html/FSTCW_FNSTCW.html">FNSTCW</a></td><td>Store x87 FPU Control Word</td><td></td></tr>
<tr><td><a href="./html/FSTENV_FNSTENV.html">FNSTENV</a></td><td>Store x87 FPU Environment</td><td></td></tr>
<tr><td><a href="./html/FSTSW_FNSTSW.html">FNSTSW</a></td><td>Store x87 FPU Status Word</td><td></td></tr>
<tr><td><a href="./html/FPATAN.html">FPATAN</a></td><td>Partial Arctangent</td><td></td></tr>
<tr><td><a href="./html/FPREM.html">FPREM</a></td><td>Partial Remainder</td><td></td></tr>
<tr><td><a href="./html/FPREM1.html">FPREM1</a></td><td>Partial Remainder</td><td></td></tr>
<tr><td><a href="./html/FPTAN.html">FPTAN</a></td><td>Partial Tangent</td><td></td></tr>
<tr><td><a href="./html/FRNDINT.html">FRNDINT</a></td><td>Round to Integer</td><td></td></tr>
<tr><td><a href="./html/FRSTOR.html">FRSTOR</a></td><td>Restore x87 FPU State</td><td></td></tr>
<tr><td><a href="./html/FSAVE_FNSAVE.html">FSAVE</a></td><td>Store x87 FPU State</td><td></td></tr>
<tr><td><a href="./html/FSCALE.html">FSCALE</a></td><td>Scale</td><td></td></tr>
<tr><td><a href="./html/FSIN.html">FSIN</a></td><td>Sine</td><td></td></tr>
<tr><td><a href="./html/FSINCOS.html">FSINCOS</a></td><td>Sine and Cosine</td><td></td></tr>
<tr><td><a href="./html/FSQRT.html">FSQRT</a></td><td>Square Root</td><td></td></tr>
<tr><td><a href="./html/FST_FSTP.html">FST</a></td><td>Store Floating Point Value</td><td></td></tr>
<tr><td><a href="./html/FSTCW_FNSTCW.html">FSTCW</a></td><td>Store x87 FPU Control Word</td><td></td></tr>
<tr><td><a href="./html/FSTENV_FNSTENV.html">FSTENV</a></td><td>Store x87 FPU Environment</td><td></td></tr>
<tr><td><a href="./html/FST_FSTP.html">FSTP</a></td><td>Store Floating Point Value</td><td></td></tr>
<tr><td><a href="./html/FSTSW_FNSTSW.html">FSTSW</a></td><td>Store x87 FPU Status Word</td><td></td></tr>
<tr><td><a href="./html/FSUB_FSUBP_FISUB.html">FSUB</a></td><td>Subtract</td><td></td></tr>
<tr><td><a href="./html/FSUB_FSUBP_FISUB.html">FSUBP</a></td><td>Subtract</td><td></td></tr>
<tr><td><a href="./html/FSUBR_FSUBRP_FISUBR.html">FSUBR</a></td><td>Reverse Subtract</td><td></td></tr>
<tr><td><a href="./html/FSUBR_FSUBRP_FISUBR.html">FSUBRP</a></td><td>Reverse Subtract</td><td></td></tr>
<tr><td><a href="./html/FTST.html">FTST</a></td><td>TEST</td><td></td></tr>
<tr><td><a href="./html/FUCOM_FUCOMP_FUCOMPP.html">FUCOM</a></td><td>Unordered Compare Floating Point Values</td><td></td></tr>
<tr><td><a href="./html/FCOMI_FCOMIP_FUCOMI_FUCOMIP.html">FUCOMI</a></td><td>Compare Floating Point Values and Set EFLAGS</td><td></td></tr>
<tr><td><a href="./html/FCOMI_FCOMIP_FUCOMI_FUCOMIP.html">FUCOMIP</a></td><td>Compare Floating Point Values and Set EFLAGS</td><td></td></tr>
<tr><td><a href="./html/FUCOM_FUCOMP_FUCOMPP.html">FUCOMP</a></td><td>Unordered Compare Floating Point Values</td><td></td></tr>
<tr><td><a href="./html/FUCOM_FUCOMP_FUCOMPP.html">FUCOMPP</a></td><td>Unordered Compare Floating Point Values</td><td></td></tr>
<tr><td><a href="./html/WAIT_FWAIT.html">FWAIT</a></td><td>Wait</td><td></td></tr>
<tr><td><a href="./html/FXAM.html">FXAM</a></td><td>Examine Floating-Point</td><td></td></tr>
<tr><td><a href="./html/FXCH.html">FXCH</a></td><td>Exchange Register Contents</td><td></td></tr>
<tr><td><a href="./html/FXRSTOR.html">FXRSTOR</a></td><td>Restore x87 FPU, MMX, XMM, and MXCSR State</td><td></td></tr>
<tr><td><a href="./html/FXSAVE.html">FXSAVE</a></td><td>Save x87 FPU, MMX Technology, and SSE State</td><td></td></tr>
<tr><td><a href="./html/FXTRACT.html">FXTRACT</a></td><td>Extract Exponent and Significand</td><td></td></tr>
<tr><td><a href="./html/FYL2X.html">FYL2X</a></td><td>Compute y ∗ log2x</td><td></td></tr>
<tr><td><a href="./html/FYL2XP1.html">FYL2XP1</a></td><td>Compute y ∗ log2(x +1)</td><td></td></tr>
<tr><td><a href="./html/HADDPD.html">HADDPD</a></td><td>Packed Double-FP Horizontal Add</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/HADDPS.html">HADDPS</a></td><td>Packed Single-FP Horizontal Add</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/HLT.html">HLT</a></td><td>Halt</td><td></td></tr>
<tr><td><a href="./html/HSUBPD.html">HSUBPD</a></td><td>Packed Double-FP Horizontal Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/HSUBPS.html">HSUBPS</a></td><td>Packed Single-FP Horizontal Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/IDIV.html">IDIV</a></td><td>Signed Divide</td><td></td></tr>
<tr><td><a href="./html/IMUL.html">IMUL</a></td><td>Signed Multiply</td><td></td></tr>
<tr><td><a href="./html/IN.html">IN</a></td><td>Input from Port</td><td></td></tr>
<tr><td><a href="./html/INC.html">INC</a></td><td>Increment by 1</td><td></td></tr>
<tr><td><a href="./html/INS_INSB_INSW_INSD.html">INS</a></td><td>Input from Port to String</td><td></td></tr>
<tr><td><a href="./html/INS_INSB_INSW_INSD.html">INSB</a></td><td>Input from Port to String</td><td></td></tr>
<tr><td><a href="./html/INS_INSB_INSW_INSD.html">INSD</a></td><td>Input from Port to String</td><td></td></tr>
<tr><td><a href="./html/INSERTPS.html">INSERTPS</a></td><td>Insert Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE4_1</td></tr>
<tr><td><a href="./html/INS_INSB_INSW_INSD.html">INSW</a></td><td>Input from Port to String</td><td></td></tr>
<tr><td><a href="./html/INT n_INTO_INT 3.html">INT</a></td><td>Call to Interrupt Procedure</td><td></td></tr>
<tr><td><a href="./html/INT n_INTO_INT 3.html">INT 3</a></td><td>Call to Interrupt Procedure</td><td></td></tr>
<tr><td><a href="./html/INT n_INTO_INT 3.html">INTO</a></td><td>Call to Interrupt Procedure</td><td></td></tr>
<tr><td><a href="./html/INVD.html">INVD</a></td><td>Invalidate Internal Caches</td><td></td></tr>
<tr><td><a href="./html/INVLPG.html">INVLPG</a></td><td>Invalidate TLB Entries</td><td></td></tr>
<tr><td><a href="./html/INVPCID.html">INVPCID</a></td><td>Invalidate Process-Context Identifier</td><td>INVPCID</td></tr>
<tr><td><a href="./html/IRET_IRETD.html">IRET</a></td><td>Interrupt Return</td><td></td></tr>
<tr><td><a href="./html/IRET_IRETD.html">IRETD</a></td><td>Interrupt Return</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JA</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JAE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JB</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JBE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JC</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JCXZ</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JECXZ</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JG</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JGE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JL</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JLE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/JMP.html">JMP</a></td><td>Jump</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNA</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNAE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNB</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNBE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNC</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNG</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNGE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNL</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNLE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNO</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNP</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNS</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JNZ</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JO</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JP</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JPE</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JPO</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JRCXZ</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JS</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/Jcc.html">JZ</a></td><td>Jump if Condition Is Met</td><td></td></tr>
<tr><td><a href="./html/KADDW_KADDB_KADDQ_KADDD.html">KADDB</a></td><td>ADD Two Masks</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KADDW_KADDB_KADDQ_KADDD.html">KADDD</a></td><td>ADD Two Masks</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KADDW_KADDB_KADDQ_KADDD.html">KADDQ</a></td><td>ADD Two Masks</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KADDW_KADDB_KADDQ_KADDD.html">KADDW</a></td><td>ADD Two Masks</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KANDW_KANDB_KANDQ_KANDD.html">KANDB</a></td><td>Bitwise Logical AND Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KANDW_KANDB_KANDQ_KANDD.html">KANDD</a></td><td>Bitwise Logical AND Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KANDNW_KANDNB_KANDNQ_KANDND.html">KANDNB</a></td><td>Bitwise Logical AND NOT Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KANDNW_KANDNB_KANDNQ_KANDND.html">KANDND</a></td><td>Bitwise Logical AND NOT Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KANDNW_KANDNB_KANDNQ_KANDND.html">KANDNQ</a></td><td>Bitwise Logical AND NOT Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KANDNW_KANDNB_KANDNQ_KANDND.html">KANDNW</a></td><td>Bitwise Logical AND NOT Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KANDW_KANDB_KANDQ_KANDD.html">KANDQ</a></td><td>Bitwise Logical AND Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KANDW_KANDB_KANDQ_KANDD.html">KANDW</a></td><td>Bitwise Logical AND Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KMOVW_KMOVB_KMOVQ_KMOVD.html">KMOVB</a></td><td>Move from and to Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KMOVW_KMOVB_KMOVQ_KMOVD.html">KMOVD</a></td><td>Move from and to Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KMOVW_KMOVB_KMOVQ_KMOVD.html">KMOVQ</a></td><td>Move from and to Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KMOVW_KMOVB_KMOVQ_KMOVD.html">KMOVW</a></td><td>Move from and to Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KNOTW_KNOTB_KNOTQ_KNOTD.html">KNOTB</a></td><td>NOT Mask Register</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KNOTW_KNOTB_KNOTQ_KNOTD.html">KNOTD</a></td><td>NOT Mask Register</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KNOTW_KNOTB_KNOTQ_KNOTD.html">KNOTQ</a></td><td>NOT Mask Register</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KNOTW_KNOTB_KNOTQ_KNOTD.html">KNOTW</a></td><td>NOT Mask Register</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORW_KORB_KORQ_KORD.html">KORB</a></td><td>Bitwise Logical OR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORW_KORB_KORQ_KORD.html">KORD</a></td><td>Bitwise Logical OR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORW_KORB_KORQ_KORD.html">KORQ</a></td><td>Bitwise Logical OR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORTESTW_KORTESTB_KORTESTQ_KORTESTD.html">KORTESTB</a></td><td>OR Masks And Set Flags</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORTESTW_KORTESTB_KORTESTQ_KORTESTD.html">KORTESTD</a></td><td>OR Masks And Set Flags</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORTESTW_KORTESTB_KORTESTQ_KORTESTD.html">KORTESTQ</a></td><td>OR Masks And Set Flags</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORTESTW_KORTESTB_KORTESTQ_KORTESTD.html">KORTESTW</a></td><td>OR Masks And Set Flags</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KORW_KORB_KORQ_KORD.html">KORW</a></td><td>Bitwise Logical OR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTLW_KSHIFTLB_KSHIFTLQ_KSHIFTLD.html">KSHIFTLB</a></td><td>Shift Left Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTLW_KSHIFTLB_KSHIFTLQ_KSHIFTLD.html">KSHIFTLD</a></td><td>Shift Left Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTLW_KSHIFTLB_KSHIFTLQ_KSHIFTLD.html">KSHIFTLQ</a></td><td>Shift Left Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTLW_KSHIFTLB_KSHIFTLQ_KSHIFTLD.html">KSHIFTLW</a></td><td>Shift Left Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTRW_KSHIFTRB_KSHIFTRQ_KSHIFTRD.html">KSHIFTRB</a></td><td>Shift Right Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTRW_KSHIFTRB_KSHIFTRQ_KSHIFTRD.html">KSHIFTRD</a></td><td>Shift Right Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTRW_KSHIFTRB_KSHIFTRQ_KSHIFTRD.html">KSHIFTRQ</a></td><td>Shift Right Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KSHIFTRW_KSHIFTRB_KSHIFTRQ_KSHIFTRD.html">KSHIFTRW</a></td><td>Shift Right Mask Registers</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KTESTW_KTESTB_KTESTQ_KTESTD.html">KTESTB</a></td><td>Packed Bit Test Masks and Set Flags</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KTESTW_KTESTB_KTESTQ_KTESTD.html">KTESTD</a></td><td>Packed Bit Test Masks and Set Flags</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KTESTW_KTESTB_KTESTQ_KTESTD.html">KTESTQ</a></td><td>Packed Bit Test Masks and Set Flags</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KTESTW_KTESTB_KTESTQ_KTESTD.html">KTESTW</a></td><td>Packed Bit Test Masks and Set Flags</td><td>AVX512BW, AVX512DQ</td></tr>
<tr><td><a href="./html/KUNPCKBW_KUNPCKWD_KUNPCKDQ.html">KUNPCKBW</a></td><td>Unpack for Mask Registers</td><td>AVX512BW, AVX512F</td></tr>
<tr><td><a href="./html/KUNPCKBW_KUNPCKWD_KUNPCKDQ.html">KUNPCKDQ</a></td><td>Unpack for Mask Registers</td><td>AVX512BW, AVX512F</td></tr>
<tr><td><a href="./html/KUNPCKBW_KUNPCKWD_KUNPCKDQ.html">KUNPCKWD</a></td><td>Unpack for Mask Registers</td><td>AVX512BW, AVX512F</td></tr>
<tr><td><a href="./html/KXNORW_KXNORB_KXNORQ_KXNORD.html">KXNORB</a></td><td>Bitwise Logical XNOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KXNORW_KXNORB_KXNORQ_KXNORD.html">KXNORD</a></td><td>Bitwise Logical XNOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KXNORW_KXNORB_KXNORQ_KXNORD.html">KXNORQ</a></td><td>Bitwise Logical XNOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KXNORW_KXNORB_KXNORQ_KXNORD.html">KXNORW</a></td><td>Bitwise Logical XNOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KXORW_KXORB_KXORQ_KXORD.html">KXORB</a></td><td>Bitwise Logical XOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KXORW_KXORB_KXORQ_KXORD.html">KXORD</a></td><td>Bitwise Logical XOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KXORW_KXORB_KXORQ_KXORD.html">KXORQ</a></td><td>Bitwise Logical XOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/KXORW_KXORB_KXORQ_KXORD.html">KXORW</a></td><td>Bitwise Logical XOR Masks</td><td>AVX512BW, AVX512DQ, AVX512F</td></tr>
<tr><td><a href="./html/LAHF.html">LAHF</a></td><td>Load Status Flags into AH Register</td><td></td></tr>
<tr><td><a href="./html/LAR.html">LAR</a></td><td>Load Access Rights Byte</td><td></td></tr>
<tr><td><a href="./html/LDDQU.html">LDDQU</a></td><td>Load Unaligned Integer 128 Bits</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/LDMXCSR.html">LDMXCSR</a></td><td>Load MXCSR Register</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/LDS_LES_LFS_LGS_LSS.html">LDS</a></td><td>Load Far Pointer</td><td></td></tr>
<tr><td><a href="./html/LEA.html">LEA</a></td><td>Load Effective Address</td><td></td></tr>
<tr><td><a href="./html/LEAVE.html">LEAVE</a></td><td>High Level Procedure Exit</td><td></td></tr>
<tr><td><a href="./html/LDS_LES_LFS_LGS_LSS.html">LES</a></td><td>Load Far Pointer</td><td></td></tr>
<tr><td><a href="./html/LFENCE.html">LFENCE</a></td><td>Load Fence</td><td></td></tr>
<tr><td><a href="./html/LDS_LES_LFS_LGS_LSS.html">LFS</a></td><td>Load Far Pointer</td><td></td></tr>
<tr><td><a href="./html/LGDT_LIDT.html">LGDT</a></td><td>Load Global/Interrupt Descriptor Table Register</td><td></td></tr>
<tr><td><a href="./html/LDS_LES_LFS_LGS_LSS.html">LGS</a></td><td>Load Far Pointer</td><td></td></tr>
<tr><td><a href="./html/LGDT_LIDT.html">LIDT</a></td><td>Load Global/Interrupt Descriptor Table Register</td><td></td></tr>
<tr><td><a href="./html/LLDT.html">LLDT</a></td><td>Load Local Descriptor Table Register</td><td></td></tr>
<tr><td><a href="./html/LMSW.html">LMSW</a></td><td>Load Machine Status Word</td><td></td></tr>
<tr><td><a href="./html/LOCK.html">LOCK</a></td><td>Assert LOCK# Signal Prefix</td><td></td></tr>
<tr><td><a href="./html/LODS_LODSB_LODSW_LODSD_LODSQ.html">LODS</a></td><td>Load String</td><td></td></tr>
<tr><td><a href="./html/LODS_LODSB_LODSW_LODSD_LODSQ.html">LODSB</a></td><td>Load String</td><td></td></tr>
<tr><td><a href="./html/LODS_LODSB_LODSW_LODSD_LODSQ.html">LODSD</a></td><td>Load String</td><td></td></tr>
<tr><td><a href="./html/LODS_LODSB_LODSW_LODSD_LODSQ.html">LODSQ</a></td><td>Load String</td><td></td></tr>
<tr><td><a href="./html/LODS_LODSB_LODSW_LODSD_LODSQ.html">LODSW</a></td><td>Load String</td><td></td></tr>
<tr><td><a href="./html/LOOP_LOOPcc.html">LOOP</a></td><td>Loop According to ECX Counter</td><td></td></tr>
<tr><td><a href="./html/LOOP_LOOPcc.html">LOOPE</a></td><td>Loop According to ECX Counter</td><td></td></tr>
<tr><td><a href="./html/LOOP_LOOPcc.html">LOOPNE</a></td><td>Loop According to ECX Counter</td><td></td></tr>
<tr><td><a href="./html/LOOP_LOOPcc.html">LOOPNZ</a></td><td>Loop According to ECX Counter</td><td></td></tr>
<tr><td><a href="./html/LOOP_LOOPcc.html">LOOPZ</a></td><td>Loop According to ECX Counter</td><td></td></tr>
<tr><td><a href="./html/LSL.html">LSL</a></td><td>Load Segment Limit</td><td></td></tr>
<tr><td><a href="./html/LDS_LES_LFS_LGS_LSS.html">LSS</a></td><td>Load Far Pointer</td><td></td></tr>
<tr><td><a href="./html/LTR.html">LTR</a></td><td>Load Task Register</td><td></td></tr>
<tr><td><a href="./html/LZCNT.html">LZCNT</a></td><td>Count the Number of Leading Zero Bits</td><td>LZCNT</td></tr>
<tr><td><a href="./html/MASKMOVDQU.html">MASKMOVDQU</a></td><td>Store Selected Bytes of Double Quadword</td><td>AVX, SSE2</td></tr>
<tr><td><a href="./html/MASKMOVQ.html">MASKMOVQ</a></td><td>Store Selected Bytes of Quadword</td><td></td></tr>
<tr><td><a href="./html/MAXPD.html">MAXPD</a></td><td>Maximum of Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MAXPS.html">MAXPS</a></td><td>Maximum of Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MAXSD.html">MAXSD</a></td><td>Return Maximum Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MAXSS.html">MAXSS</a></td><td>Return Maximum Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MFENCE.html">MFENCE</a></td><td>Memory Fence</td><td></td></tr>
<tr><td><a href="./html/MINPD.html">MINPD</a></td><td>Minimum of Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MINPS.html">MINPS</a></td><td>Minimum of Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MINSD.html">MINSD</a></td><td>Return Minimum Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MINSS.html">MINSS</a></td><td>Return Minimum Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MONITOR.html">MONITOR</a></td><td>Set Up Monitor Address</td><td></td></tr>
<tr><td><a href="./html/MOV.html">MOV</a></td><td>Move</td><td></td></tr>
<tr><td><a href="./html/MOVAPD.html">MOVAPD</a></td><td>Move Aligned Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVAPS.html">MOVAPS</a></td><td>Move Aligned Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MOVBE.html">MOVBE</a></td><td>Move Data After Swapping Bytes</td><td></td></tr>
<tr><td><a href="./html/MOVD_MOVQ.html">MOVD</a></td><td>Move Doubleword/Move Quadword</td><td>AVX, AVX512F, MMX, SSE2</td></tr>
<tr><td><a href="./html/MOVDDUP.html">MOVDDUP</a></td><td>Replicate Double FP Values</td><td>AVX, AVX512F, AVX512VL, SSE3</td></tr>
<tr><td><a href="./html/MOVDQ2Q.html">MOVDQ2Q</a></td><td>Move Quadword from XMM to MMX Technology Register</td><td></td></tr>
<tr><td><a href="./html/MOVDQA,VMOVDQA32_64.html">MOVDQA</a></td><td>Move Aligned Packed Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQU,VMOVDQU8_16_32_64.html">MOVDQU</a></td><td>Move Unaligned Packed Integer Values</td><td>AVX, AVX512BW, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVHLPS.html">MOVHLPS</a></td><td>Move Packed Single-Precision Floating-Point Values High to Low</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVHPD.html">MOVHPD</a></td><td>Move High Packed Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MOVHPS.html">MOVHPS</a></td><td>Move High Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVLHPS.html">MOVLHPS</a></td><td>Move Packed Single-Precision Floating-Point Values Low to High</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVLPD.html">MOVLPD</a></td><td>Move Low Packed Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MOVLPS.html">MOVLPS</a></td><td>Move Low Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVMSKPD.html">MOVMSKPD</a></td><td>Extract Packed Double-Precision Floating-Point Sign Mask</td><td>AVX, SSE2</td></tr>
<tr><td><a href="./html/MOVMSKPS.html">MOVMSKPS</a></td><td>Extract Packed Single-Precision Floating-Point Sign Mask</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/MOVNTDQ.html">MOVNTDQ</a></td><td>Store Packed Integers Using Non-Temporal Hint</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVNTDQA.html">MOVNTDQA</a></td><td>Load Double Quadword Non-Temporal Aligned Hint</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/MOVNTI.html">MOVNTI</a></td><td>Store Doubleword Using Non-Temporal Hint</td><td></td></tr>
<tr><td><a href="./html/MOVNTPD.html">MOVNTPD</a></td><td>Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVNTPS.html">MOVNTPS</a></td><td>Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MOVNTQ.html">MOVNTQ</a></td><td>Store of Quadword Using Non-Temporal Hint</td><td></td></tr>
<tr><td><a href="./html/MOVQ.html">MOVQ</a></td><td>Move Quadword</td><td>AVX, AVX512F, MMX, SSE2</td></tr>
<tr><td><a href="./html/MOVQ2DQ.html">MOVQ2DQ</a></td><td>Move Quadword from MMX Technology to XMM Register</td><td></td></tr>
<tr><td><a href="./html/MOVS_MOVSB_MOVSW_MOVSD_MOVSQ.html">MOVS</a></td><td>Move Data from String to String</td><td></td></tr>
<tr><td><a href="./html/MOVS_MOVSB_MOVSW_MOVSD_MOVSQ.html">MOVSB</a></td><td>Move Data from String to String</td><td></td></tr>
<tr><td><a href="./html/MOVS_MOVSB_MOVSW_MOVSD_MOVSQ.html">MOVSD</a></td><td>Move Data from String to String</td><td></td></tr>
<tr><td><a href="./html/MOVSHDUP.html">MOVSHDUP</a></td><td>Replicate Single FP Values</td><td>AVX, AVX512F, AVX512VL, SSE3</td></tr>
<tr><td><a href="./html/MOVSLDUP.html">MOVSLDUP</a></td><td>Replicate Single FP Values</td><td>AVX, AVX512F, AVX512VL, SSE3</td></tr>
<tr><td><a href="./html/MOVS_MOVSB_MOVSW_MOVSD_MOVSQ.html">MOVSQ</a></td><td>Move Data from String to String</td><td></td></tr>
<tr><td><a href="./html/MOVSS.html">MOVSS</a></td><td>Move or Merge Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVS_MOVSB_MOVSW_MOVSD_MOVSQ.html">MOVSW</a></td><td>Move Data from String to String</td><td></td></tr>
<tr><td><a href="./html/MOVSX_MOVSXD.html">MOVSX</a></td><td>Move with Sign-Extension</td><td></td></tr>
<tr><td><a href="./html/MOVSX_MOVSXD.html">MOVSXD</a></td><td>Move with Sign-Extension</td><td></td></tr>
<tr><td><a href="./html/MOVUPD.html">MOVUPD</a></td><td>Move Unaligned Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVUPS.html">MOVUPS</a></td><td>Move Unaligned Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MOVZX.html">MOVZX</a></td><td>Move with Zero-Extend</td><td></td></tr>
<tr><td><a href="./html/MPSADBW.html">MPSADBW</a></td><td>Compute Multiple Packed Sums of Absolute Difference</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/MUL.html">MUL</a></td><td>Unsigned Multiply</td><td></td></tr>
<tr><td><a href="./html/MULPD.html">MULPD</a></td><td>Multiply Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MULPS.html">MULPS</a></td><td>Multiply Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MULSD.html">MULSD</a></td><td>Multiply Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MULSS.html">MULSS</a></td><td>Multiply Scalar Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MULX.html">MULX</a></td><td>Unsigned Multiply Without Affecting Flags</td><td>BMI2</td></tr>
<tr><td><a href="./html/MWAIT.html">MWAIT</a></td><td>Monitor Wait</td><td></td></tr>
<tr><td><a href="./html/NEG.html">NEG</a></td><td>Two's Complement Negation</td><td></td></tr>
<tr><td><a href="./html/NOP.html">NOP</a></td><td>No Operation</td><td></td></tr>
<tr><td><a href="./html/NOT.html">NOT</a></td><td>One's Complement Negation</td><td></td></tr>
<tr><td><a href="./html/OR.html">OR</a></td><td>Logical Inclusive OR</td><td></td></tr>
<tr><td><a href="./html/ORPD.html">ORPD</a></td><td>Bitwise Logical OR of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ORPS.html">ORPS</a></td><td>Bitwise Logical OR of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/OUT.html">OUT</a></td><td>Output to Port</td><td></td></tr>
<tr><td><a href="./html/OUTS_OUTSB_OUTSW_OUTSD.html">OUTS</a></td><td>Output String to Port</td><td></td></tr>
<tr><td><a href="./html/OUTS_OUTSB_OUTSW_OUTSD.html">OUTSB</a></td><td>Output String to Port</td><td></td></tr>
<tr><td><a href="./html/OUTS_OUTSB_OUTSW_OUTSD.html">OUTSD</a></td><td>Output String to Port</td><td></td></tr>
<tr><td><a href="./html/OUTS_OUTSB_OUTSW_OUTSD.html">OUTSW</a></td><td>Output String to Port</td><td></td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">PABSB</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">PABSD</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">PABSQ</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">PABSW</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PACKSSWB_PACKSSDW.html">PACKSSDW</a></td><td>Pack with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PACKSSWB_PACKSSDW.html">PACKSSWB</a></td><td>Pack with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PACKUSDW.html">PACKUSDW</a></td><td>Pack with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PACKUSWB.html">PACKUSWB</a></td><td>Pack with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">PADDB</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">PADDD</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">PADDQ</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDSB_PADDSW.html">PADDSB</a></td><td>Add Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDSB_PADDSW.html">PADDSW</a></td><td>Add Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDUSB_PADDUSW.html">PADDUSB</a></td><td>Add Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDUSB_PADDUSW.html">PADDUSW</a></td><td>Add Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">PADDW</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PALIGNR.html">PALIGNR</a></td><td>Packed Align Right</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PAND.html">PAND</a></td><td>Logical AND</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PANDN.html">PANDN</a></td><td>Logical AND NOT</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PAUSE.html">PAUSE</a></td><td>Spin Loop Hint</td><td></td></tr>
<tr><td><a href="./html/PAVGB_PAVGW.html">PAVGB</a></td><td>Average Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/PAVGB_PAVGW.html">PAVGW</a></td><td>Average Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/PBLENDVB.html">PBLENDVB</a></td><td>Variable Blend Packed Bytes</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PBLENDW.html">PBLENDW</a></td><td>Blend Packed Words</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PCLMULQDQ.html">PCLMULQDQ</a></td><td>PCLMULQDQ - Carry-Less Multiplication Quadword </td><td>AVX, PCLMULQDQ</td></tr>
<tr><td><a href="./html/PCMPEQB_PCMPEQW_PCMPEQD.html">PCMPEQB</a></td><td>Compare Packed Data for Equal</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPEQB_PCMPEQW_PCMPEQD.html">PCMPEQD</a></td><td>Compare Packed Data for Equal</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPEQQ.html">PCMPEQQ</a></td><td>Compare Packed Qword Data for Equal</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PCMPEQB_PCMPEQW_PCMPEQD.html">PCMPEQW</a></td><td>Compare Packed Data for Equal</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPESTRI.html">PCMPESTRI</a></td><td>Packed Compare Explicit Length Strings, Return Index</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPESTRM.html">PCMPESTRM</a></td><td>Packed Compare Explicit Length Strings, Return Mask</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPGTB_PCMPGTW_PCMPGTD.html">PCMPGTB</a></td><td>Compare Packed Signed Integers for Greater Than</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPGTB_PCMPGTW_PCMPGTD.html">PCMPGTD</a></td><td>Compare Packed Signed Integers for Greater Than</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPGTQ.html">PCMPGTQ</a></td><td>Compare Packed Data for Greater Than</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPGTB_PCMPGTW_PCMPGTD.html">PCMPGTW</a></td><td>Compare Packed Signed Integers for Greater Than</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPISTRI.html">PCMPISTRI</a></td><td>Packed Compare Implicit Length Strings, Return Index</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPISTRM.html">PCMPISTRM</a></td><td>Packed Compare Implicit Length Strings, Return Mask</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/PDEP.html">PDEP</a></td><td>Parallel Bits Deposit</td><td>BMI2</td></tr>
<tr><td><a href="./html/PEXT.html">PEXT</a></td><td>Parallel Bits Extract</td><td>BMI2</td></tr>
<tr><td><a href="./html/PEXTRB_PEXTRD_PEXTRQ.html">PEXTRB</a></td><td>Extract Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PEXTRB_PEXTRD_PEXTRQ.html">PEXTRD</a></td><td>Extract Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PEXTRB_PEXTRD_PEXTRQ.html">PEXTRQ</a></td><td>Extract Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PEXTRW.html">PEXTRW</a></td><td>Extract Word</td><td>AVX, AVX512BW, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PHADDW_PHADDD.html">PHADDD</a></td><td>Packed Horizontal Add</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHADDSW.html">PHADDSW</a></td><td>Packed Horizontal Add and Saturate</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHADDW_PHADDD.html">PHADDW</a></td><td>Packed Horizontal Add</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHMINPOSUW.html">PHMINPOSUW</a></td><td>Packed Horizontal Word Minimum</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/PHSUBW_PHSUBD.html">PHSUBD</a></td><td>Packed Horizontal Subtract</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHSUBSW.html">PHSUBSW</a></td><td>Packed Horizontal Subtract and Saturate</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHSUBW_PHSUBD.html">PHSUBW</a></td><td>Packed Horizontal Subtract</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PINSRB_PINSRD_PINSRQ.html">PINSRB</a></td><td>Insert Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PINSRB_PINSRD_PINSRQ.html">PINSRD</a></td><td>Insert Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PINSRB_PINSRD_PINSRQ.html">PINSRQ</a></td><td>Insert Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PINSRW.html">PINSRW</a></td><td>Insert Word</td><td>AVX, AVX512BW, SSE, SSE2</td></tr>
<tr><td><a href="./html/PMADDUBSW.html">PMADDUBSW</a></td><td>Multiply and Add Packed Signed and Unsigned Bytes</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PMADDWD.html">PMADDWD</a></td><td>Multiply and Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">PMAXSB</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">PMAXSD</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">PMAXSQ</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">PMAXSW</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUB_PMAXUW.html">PMAXUB</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUD_PMAXUQ.html">PMAXUD</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUD_PMAXUQ.html">PMAXUQ</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUB_PMAXUW.html">PMAXUW</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSB_PMINSW.html">PMINSB</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSD_PMINSQ.html">PMINSD</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSD_PMINSQ.html">PMINSQ</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSB_PMINSW.html">PMINSW</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUB_PMINUW.html">PMINUB</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUD_PMINUQ.html">PMINUD</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUD_PMINUQ.html">PMINUQ</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUB_PMINUW.html">PMINUW</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVMSKB.html">PMOVMSKB</a></td><td>Move Byte Mask</td><td>AVX, AVX2, SSE, SSE2</td></tr>
<tr><td><a href="./html/PMOVSX.html">PMOVSXBD</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">PMOVSXBQ</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">PMOVSXBW</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">PMOVSXDQ</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">PMOVSXWD</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">PMOVSXWQ</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">PMOVZXBD</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">PMOVZXBQ</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">PMOVZXBW</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">PMOVZXDQ</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">PMOVZXWD</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">PMOVZXWQ</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMULDQ.html">PMULDQ</a></td><td>Multiply Packed Doubleword Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMULHRSW.html">PMULHRSW</a></td><td>Packed Multiply High with Round and Scale</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PMULHUW.html">PMULHUW</a></td><td>Multiply Packed Unsigned Integers and Store High Result</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/PMULHW.html">PMULHW</a></td><td>Multiply Packed Signed Integers and Store High Result</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PMULLD_PMULLQ.html">PMULLD</a></td><td>Multiply Packed Integers and Store Low Result</td><td>AVX, AVX2, AVX512DQ, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMULLD_PMULLQ.html">PMULLQ</a></td><td>Multiply Packed Integers and Store Low Result</td><td>AVX, AVX2, AVX512DQ, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMULLW.html">PMULLW</a></td><td>Multiply Packed Signed Integers and Store Low Result</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PMULUDQ.html">PMULUDQ</a></td><td>Multiply Packed Unsigned Doubleword Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/POP.html">POP</a></td><td>Pop a Value from the Stack</td><td></td></tr>
<tr><td><a href="./html/POPA_POPAD.html">POPA</a></td><td>Pop All General-Purpose Registers</td><td></td></tr>
<tr><td><a href="./html/POPA_POPAD.html">POPAD</a></td><td>Pop All General-Purpose Registers</td><td></td></tr>
<tr><td><a href="./html/POPCNT.html">POPCNT</a></td><td>Return the Count of Number of Bits Set to 1</td><td></td></tr>
<tr><td><a href="./html/POPF_POPFD_POPFQ.html">POPF</a></td><td>Pop Stack into EFLAGS Register</td><td></td></tr>
<tr><td><a href="./html/POPF_POPFD_POPFQ.html">POPFD</a></td><td>Pop Stack into EFLAGS Register</td><td></td></tr>
<tr><td><a href="./html/POPF_POPFD_POPFQ.html">POPFQ</a></td><td>Pop Stack into EFLAGS Register</td><td></td></tr>
<tr><td><a href="./html/POR.html">POR</a></td><td>Bitwise Logical OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PREFETCHh.html">PREFETCHNTA</a></td><td>Prefetch Data Into Caches</td><td></td></tr>
<tr><td><a href="./html/PREFETCHh.html">PREFETCHT0</a></td><td>Prefetch Data Into Caches</td><td></td></tr>
<tr><td><a href="./html/PREFETCHh.html">PREFETCHT1</a></td><td>Prefetch Data Into Caches</td><td></td></tr>
<tr><td><a href="./html/PREFETCHh.html">PREFETCHT2</a></td><td>Prefetch Data Into Caches</td><td></td></tr>
<tr><td><a href="./html/PREFETCHW.html">PREFETCHW</a></td><td>Prefetch Data into Caches in Anticipation of a Write</td><td>PRFCHW</td></tr>
<tr><td><a href="./html/PREFETCHWT1.html">PREFETCHWT1</a></td><td>Prefetch Vector Data Into Caches with Intent to Write and T1 Hint</td><td>PREFETCHWT1</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">PROLD</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">PROLQ</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">PROLVD</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">PROLVQ</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">PRORD</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">PRORQ</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">PRORVD</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">PRORVQ</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PSADBW.html">PSADBW</a></td><td>Compute Sum of Absolute Differences</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/PSHUFB.html">PSHUFB</a></td><td>Packed Shuffle Bytes</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PSHUFD.html">PSHUFD</a></td><td>Shuffle Packed Doublewords</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSHUFHW.html">PSHUFHW</a></td><td>Shuffle Packed High Words</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSHUFLW.html">PSHUFLW</a></td><td>Shuffle Packed Low Words</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSHUFW.html">PSHUFW</a></td><td>Shuffle Packed Words</td><td></td></tr>
<tr><td><a href="./html/PSIGNB_PSIGNW_PSIGND.html">PSIGNB</a></td><td>Packed SIGN</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PSIGNB_PSIGNW_PSIGND.html">PSIGND</a></td><td>Packed SIGN</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PSIGNB_PSIGNW_PSIGND.html">PSIGNW</a></td><td>Packed SIGN</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PSLLW_PSLLD_PSLLQ.html">PSLLD</a></td><td>Shift Packed Data Left Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSLLDQ.html">PSLLDQ</a></td><td>Shift Double Quadword Left Logical</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSLLW_PSLLD_PSLLQ.html">PSLLQ</a></td><td>Shift Packed Data Left Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSLLW_PSLLD_PSLLQ.html">PSLLW</a></td><td>Shift Packed Data Left Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRAW_PSRAD_PSRAQ.html">PSRAD</a></td><td>Shift Packed Data Right Arithmetic</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRAW_PSRAD_PSRAQ.html">PSRAQ</a></td><td>Shift Packed Data Right Arithmetic</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRAW_PSRAD_PSRAQ.html">PSRAW</a></td><td>Shift Packed Data Right Arithmetic</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRLW_PSRLD_PSRLQ.html">PSRLD</a></td><td>Shift Packed Data Right Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRLDQ.html">PSRLDQ</a></td><td>Shift Double Quadword Right Logical</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSRLW_PSRLD_PSRLQ.html">PSRLQ</a></td><td>Shift Packed Data Right Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRLW_PSRLD_PSRLQ.html">PSRLW</a></td><td>Shift Packed Data Right Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBB_PSUBW_PSUBD.html">PSUBB</a></td><td>Subtract Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBB_PSUBW_PSUBD.html">PSUBD</a></td><td>Subtract Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBQ.html">PSUBQ</a></td><td>Subtract Packed Quadword Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSUBSB_PSUBSW.html">PSUBSB</a></td><td>Subtract Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBSB_PSUBSW.html">PSUBSW</a></td><td>Subtract Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBUSB_PSUBUSW.html">PSUBUSB</a></td><td>Subtract Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBUSB_PSUBUSW.html">PSUBUSW</a></td><td>Subtract Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBB_PSUBW_PSUBD.html">PSUBW</a></td><td>Subtract Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PTEST.html">PTEST</a></td><td>PTEST- Logical Compare </td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/PTWRITE.html">PTWRITE</a></td><td>PTWRITE - Write Data to a Processor Trace Packet </td><td></td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">PUNPCKHBW</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">PUNPCKHDQ</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">PUNPCKHQDQ</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">PUNPCKHWD</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">PUNPCKLBW</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">PUNPCKLDQ</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">PUNPCKLQDQ</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">PUNPCKLWD</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUSH.html">PUSH</a></td><td>Push Word, Doubleword or Quadword Onto the Stack</td><td></td></tr>
<tr><td><a href="./html/PUSHA_PUSHAD.html">PUSHA</a></td><td>Push All General-Purpose Registers</td><td></td></tr>
<tr><td><a href="./html/PUSHA_PUSHAD.html">PUSHAD</a></td><td>Push All General-Purpose Registers</td><td></td></tr>
<tr><td><a href="./html/PUSHF_PUSHFD.html">PUSHF</a></td><td>Push EFLAGS Register onto the Stack</td><td></td></tr>
<tr><td><a href="./html/PUSHF_PUSHFD.html">PUSHFD</a></td><td>Push EFLAGS Register onto the Stack</td><td></td></tr>
<tr><td><a href="./html/PXOR.html">PXOR</a></td><td>Logical Exclusive OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/RCL_RCR_ROL_ROR.html">RCL</a></td><td>Rotate</td><td></td></tr>
<tr><td><a href="./html/RCPPS.html">RCPPS</a></td><td>Compute Reciprocals of Packed Single-Precision Floating-Point Values</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/RCPSS.html">RCPSS</a></td><td>Compute Reciprocal of Scalar Single-Precision Floating-Point Values</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/RCL_RCR_ROL_ROR.html">RCR</a></td><td>Rotate</td><td></td></tr>
<tr><td><a href="./html/RDFSBASE_RDGSBASE.html">RDFSBASE</a></td><td>Read FS/GS Segment Base</td><td>FSGSBASE</td></tr>
<tr><td><a href="./html/RDFSBASE_RDGSBASE.html">RDGSBASE</a></td><td>Read FS/GS Segment Base</td><td>FSGSBASE</td></tr>
<tr><td><a href="./html/RDMSR.html">RDMSR</a></td><td>Read from Model Specific Register</td><td></td></tr>
<tr><td><a href="./html/RDPID.html">RDPID</a></td><td>Read Processor ID</td><td>RDPID</td></tr>
<tr><td><a href="./html/RDPKRU.html">RDPKRU</a></td><td>Read Protection Key Rights for User Pages</td><td></td></tr>
<tr><td><a href="./html/RDPMC.html">RDPMC</a></td><td>Read Performance-Monitoring Counters</td><td></td></tr>
<tr><td><a href="./html/RDRAND.html">RDRAND</a></td><td>Read Random Number</td><td>RDRAND</td></tr>
<tr><td><a href="./html/RDSEED.html">RDSEED</a></td><td>Read Random SEED</td><td>RDSEED</td></tr>
<tr><td><a href="./html/RDTSC.html">RDTSC</a></td><td>Read Time-Stamp Counter</td><td></td></tr>
<tr><td><a href="./html/RDTSCP.html">RDTSCP</a></td><td>Read Time-Stamp Counter and Processor ID</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REP INS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REP LODS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REP MOVS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REP OUTS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REP STOS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REPE CMPS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REPE SCAS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REPNE CMPS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/REP_REPE_REPZ_REPNE_REPNZ.html">REPNE SCAS</a></td><td>Repeat String Operation Prefix</td><td></td></tr>
<tr><td><a href="./html/RET.html">RET</a></td><td>Return from Procedure</td><td></td></tr>
<tr><td><a href="./html/RCL_RCR_ROL_ROR.html">ROL</a></td><td>Rotate</td><td></td></tr>
<tr><td><a href="./html/RCL_RCR_ROL_ROR.html">ROR</a></td><td>Rotate</td><td></td></tr>
<tr><td><a href="./html/RORX.html">RORX</a></td><td>Rotate Right Logical Without Affecting Flags</td><td>BMI2</td></tr>
<tr><td><a href="./html/ROUNDPD.html">ROUNDPD</a></td><td>Round Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/ROUNDPS.html">ROUNDPS</a></td><td>Round Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/ROUNDSD.html">ROUNDSD</a></td><td>Round Scalar Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/ROUNDSS.html">ROUNDSS</a></td><td>Round Scalar Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/RSM.html">RSM</a></td><td>Resume from System Management Mode</td><td></td></tr>
<tr><td><a href="./html/RSQRTPS.html">RSQRTPS</a></td><td>Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/RSQRTSS.html">RSQRTSS</a></td><td>Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/SAHF.html">SAHF</a></td><td>Store AH into Flags</td><td></td></tr>
<tr><td><a href="./html/SAL_SAR_SHL_SHR.html">SAL</a></td><td>Shift</td><td></td></tr>
<tr><td><a href="./html/SAL_SAR_SHL_SHR.html">SAR</a></td><td>Shift</td><td></td></tr>
<tr><td><a href="./html/SARX_SHLX_SHRX.html">SARX</a></td><td>Shift Without Affecting Flags</td><td></td></tr>
<tr><td><a href="./html/SBB.html">SBB</a></td><td>Integer Subtraction with Borrow</td><td></td></tr>
<tr><td><a href="./html/SCAS_SCASB_SCASW_SCASD.html">SCAS</a></td><td>Scan String</td><td></td></tr>
<tr><td><a href="./html/SCAS_SCASB_SCASW_SCASD.html">SCASB</a></td><td>Scan String</td><td></td></tr>
<tr><td><a href="./html/SCAS_SCASB_SCASW_SCASD.html">SCASD</a></td><td>Scan String</td><td></td></tr>
<tr><td><a href="./html/SCAS_SCASB_SCASW_SCASD.html">SCASW</a></td><td>Scan String</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETA</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETAE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETB</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETBE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETC</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETG</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETGE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETL</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETLE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNA</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNAE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNB</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNBE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNC</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNG</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNGE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNL</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNO</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNP</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNS</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETNZ</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETO</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETP</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETPE</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETPO</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETS</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SETcc.html">SETZ</a></td><td>Set Byte on Condition</td><td></td></tr>
<tr><td><a href="./html/SFENCE.html">SFENCE</a></td><td>Store Fence</td><td></td></tr>
<tr><td><a href="./html/SGDT.html">SGDT</a></td><td>Store Global Descriptor Table Register</td><td></td></tr>
<tr><td><a href="./html/SHA1MSG1.html">SHA1MSG1</a></td><td>Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords</td><td>SHA</td></tr>
<tr><td><a href="./html/SHA1MSG2.html">SHA1MSG2</a></td><td>Perform a Final Calculation for the Next Four SHA1 Message Dwords</td><td>SHA</td></tr>
<tr><td><a href="./html/SHA1NEXTE.html">SHA1NEXTE</a></td><td>Calculate SHA1 State Variable E after Four Rounds</td><td>SHA</td></tr>
<tr><td><a href="./html/SHA1RNDS4.html">SHA1RNDS4</a></td><td>Perform Four Rounds of SHA1 Operation</td><td>SHA</td></tr>
<tr><td><a href="./html/SHA256MSG1.html">SHA256MSG1</a></td><td>Perform an Intermediate Calculation for the Next Four SHA256 Message Dwords</td><td>SHA</td></tr>
<tr><td><a href="./html/SHA256MSG2.html">SHA256MSG2</a></td><td>Perform a Final Calculation for the Next Four SHA256 Message Dwords</td><td>SHA</td></tr>
<tr><td><a href="./html/SHA256RNDS2.html">SHA256RNDS2</a></td><td>Perform Two Rounds of SHA256 Operation</td><td>SHA</td></tr>
<tr><td><a href="./html/SAL_SAR_SHL_SHR.html">SHL</a></td><td>Shift</td><td></td></tr>
<tr><td><a href="./html/SHLD.html">SHLD</a></td><td>Double Precision Shift Left</td><td></td></tr>
<tr><td><a href="./html/SARX_SHLX_SHRX.html">SHLX</a></td><td>Shift Without Affecting Flags</td><td></td></tr>
<tr><td><a href="./html/SAL_SAR_SHL_SHR.html">SHR</a></td><td>Shift</td><td></td></tr>
<tr><td><a href="./html/SHRD.html">SHRD</a></td><td>Double Precision Shift Right</td><td></td></tr>
<tr><td><a href="./html/SARX_SHLX_SHRX.html">SHRX</a></td><td>Shift Without Affecting Flags</td><td></td></tr>
<tr><td><a href="./html/SHUFPD.html">SHUFPD</a></td><td>Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/SHUFPS.html">SHUFPS</a></td><td>Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/SIDT.html">SIDT</a></td><td>Store Interrupt Descriptor Table Register</td><td></td></tr>
<tr><td><a href="./html/SLDT.html">SLDT</a></td><td>Store Local Descriptor Table Register</td><td></td></tr>
<tr><td><a href="./html/SMSW.html">SMSW</a></td><td>Store Machine Status Word</td><td></td></tr>
<tr><td><a href="./html/SQRTPD.html">SQRTPD</a></td><td>Square Root of Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/SQRTPS.html">SQRTPS</a></td><td>Square Root of Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/SQRTSD.html">SQRTSD</a></td><td>Compute Square Root of Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/SQRTSS.html">SQRTSS</a></td><td>Compute Square Root of Scalar Single-Precision Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/STAC.html">STAC</a></td><td>Set AC Flag in EFLAGS Register</td><td></td></tr>
<tr><td><a href="./html/STC.html">STC</a></td><td>Set Carry Flag</td><td></td></tr>
<tr><td><a href="./html/STD.html">STD</a></td><td>Set Direction Flag</td><td></td></tr>
<tr><td><a href="./html/STI.html">STI</a></td><td>Set Interrupt Flag</td><td></td></tr>
<tr><td><a href="./html/STMXCSR.html">STMXCSR</a></td><td>Store MXCSR Register State</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/STOS_STOSB_STOSW_STOSD_STOSQ.html">STOS</a></td><td>Store String</td><td></td></tr>
<tr><td><a href="./html/STOS_STOSB_STOSW_STOSD_STOSQ.html">STOSB</a></td><td>Store String</td><td></td></tr>
<tr><td><a href="./html/STOS_STOSB_STOSW_STOSD_STOSQ.html">STOSD</a></td><td>Store String</td><td></td></tr>
<tr><td><a href="./html/STOS_STOSB_STOSW_STOSD_STOSQ.html">STOSQ</a></td><td>Store String</td><td></td></tr>
<tr><td><a href="./html/STOS_STOSB_STOSW_STOSD_STOSQ.html">STOSW</a></td><td>Store String</td><td></td></tr>
<tr><td><a href="./html/STR.html">STR</a></td><td>Store Task Register</td><td></td></tr>
<tr><td><a href="./html/SUB.html">SUB</a></td><td>Subtract</td><td></td></tr>
<tr><td><a href="./html/SUBPD.html">SUBPD</a></td><td>Subtract Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/SUBPS.html">SUBPS</a></td><td>Subtract Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/SUBSD.html">SUBSD</a></td><td>Subtract Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/SUBSS.html">SUBSS</a></td><td>Subtract Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/SWAPGS.html">SWAPGS</a></td><td>Swap GS Base Register</td><td></td></tr>
<tr><td><a href="./html/SYSCALL.html">SYSCALL</a></td><td>Fast System Call</td><td></td></tr>
<tr><td><a href="./html/SYSENTER.html">SYSENTER</a></td><td>Fast System Call</td><td></td></tr>
<tr><td><a href="./html/SYSEXIT.html">SYSEXIT</a></td><td>Fast Return from Fast System Call</td><td></td></tr>
<tr><td><a href="./html/SYSRET.html">SYSRET</a></td><td>Return From Fast System Call</td><td></td></tr>
<tr><td><a href="./html/TEST.html">TEST</a></td><td>Logical Compare</td><td></td></tr>
<tr><td><a href="./html/TZCNT.html">TZCNT</a></td><td>Count the Number of Trailing Zero Bits</td><td>BMI1</td></tr>
<tr><td><a href="./html/UCOMISD.html">UCOMISD</a></td><td>Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/UCOMISS.html">UCOMISS</a></td><td>Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/UD2.html">UD2</a></td><td>Undefined Instruction</td><td></td></tr>
<tr><td><a href="./html/UNPCKHPD.html">UNPCKHPD</a></td><td>Unpack and Interleave High Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/UNPCKHPS.html">UNPCKHPS</a></td><td>Unpack and Interleave High Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/UNPCKLPD.html">UNPCKLPD</a></td><td>Unpack and Interleave Low Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/UNPCKLPS.html">UNPCKLPS</a></td><td>Unpack and Interleave Low Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/ADDPD.html">VADDPD</a></td><td>Add Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ADDPS.html">VADDPS</a></td><td>Add Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/ADDSD.html">VADDSD</a></td><td>Add Scalar Double-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/ADDSS.html">VADDSS</a></td><td>Add Scalar Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/ADDSUBPD.html">VADDSUBPD</a></td><td>Packed Double-FP Add/Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/ADDSUBPS.html">VADDSUBPS</a></td><td>Packed Single-FP Add/Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/AESDEC.html">VAESDEC</a></td><td>Perform One Round of an AES Decryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESDECLAST.html">VAESDECLAST</a></td><td>Perform Last Round of an AES Decryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESENC.html">VAESENC</a></td><td>Perform One Round of an AES Encryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESENCLAST.html">VAESENCLAST</a></td><td>Perform Last Round of an AES Encryption Flow</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESIMC.html">VAESIMC</a></td><td>Perform the AES InvMixColumn Transformation</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/AESKEYGENASSIST.html">VAESKEYGENASSIST</a></td><td>AES Round Key Generation Assist</td><td>AES, AVX</td></tr>
<tr><td><a href="./html/VALIGND_VALIGNQ.html">VALIGND</a></td><td>Align Doubleword/Quadword Vectors</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VALIGND_VALIGNQ.html">VALIGNQ</a></td><td>Align Doubleword/Quadword Vectors</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/ANDNPD.html">VANDNPD</a></td><td>Bitwise Logical AND NOT of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ANDNPS.html">VANDNPS</a></td><td>Bitwise Logical AND NOT of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/ANDPD.html">VANDPD</a></td><td>Bitwise Logical AND of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ANDPS.html">VANDPS</a></td><td>Bitwise Logical AND of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/VBLENDMPD_VBLENDMPS.html">VBLENDMPD</a></td><td>Blend Float64/Float32 Vectors Using an OpMask Control</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBLENDMPD_VBLENDMPS.html">VBLENDMPS</a></td><td>Blend Float64/Float32 Vectors Using an OpMask Control</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/BLENDPD.html">VBLENDPD</a></td><td>Blend Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/BLENDPS.html">VBLENDPS</a></td><td>Blend Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/BLENDVPD.html">VBLENDVPD</a></td><td>Variable Blend Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/BLENDVPS.html">VBLENDVPS</a></td><td>Variable Blend Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTF128</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTF32X2</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTF32X4</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTF32X8</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTF64X2</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTF64X4</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCAST.html">VBROADCASTI32X8</a></td><td>Load Integer and Broadcast</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCAST.html">VBROADCASTI32x2</a></td><td>Load Integer and Broadcast</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCAST.html">VBROADCASTI64X4</a></td><td>Load Integer and Broadcast</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTSD</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VBROADCAST.html">VBROADCASTSS</a></td><td>Load with Broadcast Floating-Point Data</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/CMPPD.html">VCMPPD</a></td><td>Compare Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CMPPS.html">VCMPPS</a></td><td>Compare Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/CMPSD.html">VCMPSD</a></td><td>Compare Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CMPSS.html">VCMPSS</a></td><td>Compare Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/COMISD.html">VCOMISD</a></td><td>Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/COMISS.html">VCOMISS</a></td><td>Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/VCOMPRESSPD.html">VCOMPRESSPD</a></td><td>Store Sparse Packed Double-Precision Floating-Point Values into Dense Memory</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VCOMPRESSPS.html">VCOMPRESSPS</a></td><td>Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/CVTDQ2PD.html">VCVTDQ2PD</a></td><td>Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTDQ2PS.html">VCVTDQ2PS</a></td><td>Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPD2DQ.html">VCVTPD2DQ</a></td><td>Convert Packed Double-Precision Floating-Point Values to Packed Doubleword Integers</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPD2PS.html">VCVTPD2PS</a></td><td>Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/VCVTPD2QQ.html">VCVTPD2QQ</a></td><td>Convert Packed Double-Precision Floating-Point Values to Packed Quadword Integers</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTPD2UDQ.html">VCVTPD2UDQ</a></td><td>Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTPD2UQQ.html">VCVTPD2UQQ</a></td><td>Convert Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTPH2PS.html">VCVTPH2PS</a></td><td>Convert 16-bit FP values to Single-Precision FP values</td><td>AVX512F, AVX512VL, F16C</td></tr>
<tr><td><a href="./html/CVTPS2DQ.html">VCVTPS2DQ</a></td><td>Convert Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/CVTPS2PD.html">VCVTPS2PD</a></td><td>Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/VCVTPS2PH.html">VCVTPS2PH</a></td><td>Convert Single-Precision FP value to 16-bit FP value</td><td>AVX512F, AVX512VL, F16C</td></tr>
<tr><td><a href="./html/VCVTPS2QQ.html">VCVTPS2QQ</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTPS2UDQ.html">VCVTPS2UDQ</a></td><td>Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTPS2UQQ.html">VCVTPS2UQQ</a></td><td>Convert Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTQQ2PD.html">VCVTQQ2PD</a></td><td>Convert Packed Quadword Integers to Packed Double-Precision Floating-Point Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTQQ2PS.html">VCVTQQ2PS</a></td><td>Convert Packed Quadword Integers to Packed Single-Precision Floating-Point Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/CVTSD2SI.html">VCVTSD2SI</a></td><td>Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTSD2SS.html">VCVTSD2SS</a></td><td>Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/VCVTSD2USI.html">VCVTSD2USI</a></td><td>Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer</td><td>AVX512F</td></tr>
<tr><td><a href="./html/CVTSI2SD.html">VCVTSI2SD</a></td><td>Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTSI2SS.html">VCVTSI2SS</a></td><td>Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/CVTSS2SD.html">VCVTSS2SD</a></td><td>Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/CVTSS2SI.html">VCVTSS2SI</a></td><td>Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/VCVTSS2USI.html">VCVTSS2USI</a></td><td>Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword Integer</td><td>AVX512F</td></tr>
<tr><td><a href="./html/CVTTPD2DQ.html">VCVTTPD2DQ</a></td><td>Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Doubleword Integers</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/VCVTTPD2QQ.html">VCVTTPD2QQ</a></td><td>Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Quadword Integers</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTTPD2UDQ.html">VCVTTPD2UDQ</a></td><td>Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Doubleword Integers</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTTPD2UQQ.html">VCVTTPD2UQQ</a></td><td>Convert with Truncation Packed Double-Precision Floating-Point Values to Packed Unsigned Quadword Integers</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/CVTTPS2DQ.html">VCVTTPS2DQ</a></td><td>Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Signed Doubleword Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/VCVTTPS2QQ.html">VCVTTPS2QQ</a></td><td>Convert with Truncation Packed Single Precision Floating-Point Values to Packed Singed Quadword Integer Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTTPS2UDQ.html">VCVTTPS2UDQ</a></td><td>Convert with Truncation Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTTPS2UQQ.html">VCVTTPS2UQQ</a></td><td>Convert with Truncation Packed Single Precision Floating-Point Values to Packed Unsigned Quadword Integer Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/CVTTSD2SI.html">VCVTTSD2SI</a></td><td>Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed Integer</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/VCVTTSD2USI.html">VCVTTSD2USI</a></td><td>Convert with Truncation Scalar Double-Precision Floating-Point Value to Unsigned Integer</td><td>AVX512F</td></tr>
<tr><td><a href="./html/CVTTSS2SI.html">VCVTTSS2SI</a></td><td>Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/VCVTTSS2USI.html">VCVTTSS2USI</a></td><td>Convert with Truncation Scalar Single-Precision Floating-Point Value to Unsigned Integer</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VCVTUDQ2PD.html">VCVTUDQ2PD</a></td><td>Convert Packed Unsigned Doubleword Integers to Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTUDQ2PS.html">VCVTUDQ2PS</a></td><td>Convert Packed Unsigned Doubleword Integers to Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTUQQ2PD.html">VCVTUQQ2PD</a></td><td>Convert Packed Unsigned Quadword Integers to Packed Double-Precision Floating-Point Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTUQQ2PS.html">VCVTUQQ2PS</a></td><td>Convert Packed Unsigned Quadword Integers to Packed Single-Precision Floating-Point Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VCVTUSI2SD.html">VCVTUSI2SD</a></td><td>Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VCVTUSI2SS.html">VCVTUSI2SS</a></td><td>Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VDBPSADBW.html">VDBPSADBW</a></td><td>Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/DIVPD.html">VDIVPD</a></td><td>Divide Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/DIVPS.html">VDIVPS</a></td><td>Divide Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/DIVSD.html">VDIVSD</a></td><td>Divide Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/DIVSS.html">VDIVSS</a></td><td>Divide Scalar Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/DPPD.html">VDPPD</a></td><td>Dot Product of Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/DPPS.html">VDPPS</a></td><td>Dot Product of Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/VERR_VERW.html">VERR</a></td><td>Verify a Segment for Reading or Writing</td><td></td></tr>
<tr><td><a href="./html/VERR_VERW.html">VERW</a></td><td>Verify a Segment for Reading or Writing</td><td></td></tr>
<tr><td><a href="./html/VEXP2PD.html">VEXP2PD</a></td><td>Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point Values with Less Than 2^-23 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VEXP2PS.html">VEXP2PS</a></td><td>Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point Values with Less Than 2^-23 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VEXPANDPD.html">VEXPANDPD</a></td><td>Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXPANDPS.html">VEXPANDPS</a></td><td>Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTF128_VEXTRACTF32x4_VEXTRACTF64x2_VEXTRACTF32x8_VEXTRACTF64x4.html">VEXTRACTF128</a></td><td>Extra ct Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTF128_VEXTRACTF32x4_VEXTRACTF64x2_VEXTRACTF32x8_VEXTRACTF64x4.html">VEXTRACTF32x4</a></td><td>Extra ct Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTF128_VEXTRACTF32x4_VEXTRACTF64x2_VEXTRACTF32x8_VEXTRACTF64x4.html">VEXTRACTF32x8</a></td><td>Extra ct Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTF128_VEXTRACTF32x4_VEXTRACTF64x2_VEXTRACTF32x8_VEXTRACTF64x4.html">VEXTRACTF64x2</a></td><td>Extra ct Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTF128_VEXTRACTF32x4_VEXTRACTF64x2_VEXTRACTF32x8_VEXTRACTF64x4.html">VEXTRACTF64x4</a></td><td>Extra ct Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTI128_VEXTRACTI32x4_VEXTRACTI64x2_VEXTRACTI32x8_VEXTRACTI64x4.html">VEXTRACTI128</a></td><td>Extract packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTI128_VEXTRACTI32x4_VEXTRACTI64x2_VEXTRACTI32x8_VEXTRACTI64x4.html">VEXTRACTI32x4</a></td><td>Extract packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTI128_VEXTRACTI32x4_VEXTRACTI64x2_VEXTRACTI32x8_VEXTRACTI64x4.html">VEXTRACTI32x8</a></td><td>Extract packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTI128_VEXTRACTI32x4_VEXTRACTI64x2_VEXTRACTI32x8_VEXTRACTI64x4.html">VEXTRACTI64x2</a></td><td>Extract packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VEXTRACTI128_VEXTRACTI32x4_VEXTRACTI64x2_VEXTRACTI32x8_VEXTRACTI64x4.html">VEXTRACTI64x4</a></td><td>Extract packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/EXTRACTPS.html">VEXTRACTPS</a></td><td>Extract Packed Floating-Point Values</td><td>AVX, AVX512F, SSE4_1</td></tr>
<tr><td><a href="./html/VFIXUPIMMPD.html">VFIXUPIMMPD</a></td><td>Fix Up Special Packed Float64 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VFIXUPIMMPS.html">VFIXUPIMMPS</a></td><td>Fix Up Special Packed Float32 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VFIXUPIMMSD.html">VFIXUPIMMSD</a></td><td>Fix Up Special Scalar Float64 Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VFIXUPIMMSS.html">VFIXUPIMMSS</a></td><td>Fix Up Special Scalar Float32 Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VFMADD132PD_VFMADD213PD_VFMADD231PD.html">VFMADD132PD</a></td><td>Fused Multiply-Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADD132PS_VFMADD213PS_VFMADD231PS.html">VFMADD132PS</a></td><td>Fused Multiply-Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADD132SD_VFMADD213SD_VFMADD231SD.html">VFMADD132SD</a></td><td>Fused Multiply-Add of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMADD132SS_VFMADD213SS_VFMADD231SS.html">VFMADD132SS</a></td><td>Fused Multiply-Add of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMADD132PD_VFMADD213PD_VFMADD231PD.html">VFMADD213PD</a></td><td>Fused Multiply-Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADD132PS_VFMADD213PS_VFMADD231PS.html">VFMADD213PS</a></td><td>Fused Multiply-Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADD132SD_VFMADD213SD_VFMADD231SD.html">VFMADD213SD</a></td><td>Fused Multiply-Add of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMADD132SS_VFMADD213SS_VFMADD231SS.html">VFMADD213SS</a></td><td>Fused Multiply-Add of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMADD132PD_VFMADD213PD_VFMADD231PD.html">VFMADD231PD</a></td><td>Fused Multiply-Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADD132PS_VFMADD213PS_VFMADD231PS.html">VFMADD231PS</a></td><td>Fused Multiply-Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADD132SD_VFMADD213SD_VFMADD231SD.html">VFMADD231SD</a></td><td>Fused Multiply-Add of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMADD132SS_VFMADD213SS_VFMADD231SS.html">VFMADD231SS</a></td><td>Fused Multiply-Add of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMADDSUB132PD_VFMADDSUB213PD_VFMADDSUB231PD.html">VFMADDSUB132PD</a></td><td>Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADDSUB132PS_VFMADDSUB213PS_VFMADDSUB231PS.html">VFMADDSUB132PS</a></td><td>Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADDSUB132PD_VFMADDSUB213PD_VFMADDSUB231PD.html">VFMADDSUB213PD</a></td><td>Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADDSUB132PS_VFMADDSUB213PS_VFMADDSUB231PS.html">VFMADDSUB213PS</a></td><td>Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADDSUB132PD_VFMADDSUB213PD_VFMADDSUB231PD.html">VFMADDSUB231PD</a></td><td>Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMADDSUB132PS_VFMADDSUB213PS_VFMADDSUB231PS.html">VFMADDSUB231PS</a></td><td>Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132PD_VFMSUB213PD_VFMSUB231PD.html">VFMSUB132PD</a></td><td>Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132PS_VFMSUB213PS_VFMSUB231PS.html">VFMSUB132PS</a></td><td>Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132SD_VFMSUB213SD_VFMSUB231SD.html">VFMSUB132SD</a></td><td>Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132SS_VFMSUB213SS_VFMSUB231SS.html">VFMSUB132SS</a></td><td>Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132PD_VFMSUB213PD_VFMSUB231PD.html">VFMSUB213PD</a></td><td>Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132PS_VFMSUB213PS_VFMSUB231PS.html">VFMSUB213PS</a></td><td>Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132SD_VFMSUB213SD_VFMSUB231SD.html">VFMSUB213SD</a></td><td>Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132SS_VFMSUB213SS_VFMSUB231SS.html">VFMSUB213SS</a></td><td>Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132PD_VFMSUB213PD_VFMSUB231PD.html">VFMSUB231PD</a></td><td>Fused Multiply-Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132PS_VFMSUB213PS_VFMSUB231PS.html">VFMSUB231PS</a></td><td>Fused Multiply-Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132SD_VFMSUB213SD_VFMSUB231SD.html">VFMSUB231SD</a></td><td>Fused Multiply-Subtract of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMSUB132SS_VFMSUB213SS_VFMSUB231SS.html">VFMSUB231SS</a></td><td>Fused Multiply-Subtract of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFMSUBADD132PD_VFMSUBADD213PD_VFMSUBADD231PD.html">VFMSUBADD132PD</a></td><td>Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUBADD132PS_VFMSUBADD213PS_VFMSUBADD231PS.html">VFMSUBADD132PS</a></td><td>Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUBADD132PD_VFMSUBADD213PD_VFMSUBADD231PD.html">VFMSUBADD213PD</a></td><td>Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUBADD132PS_VFMSUBADD213PS_VFMSUBADD231PS.html">VFMSUBADD213PS</a></td><td>Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUBADD132PD_VFMSUBADD213PD_VFMSUBADD231PD.html">VFMSUBADD231PD</a></td><td>Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFMSUBADD132PS_VFMSUBADD213PS_VFMSUBADD231PS.html">VFMSUBADD231PS</a></td><td>Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132PD_VFNMADD213PD_VFNMADD231PD.html">VFNMADD132PD</a></td><td>Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132PS_VFNMADD213PS_VFNMADD231PS.html">VFNMADD132PS</a></td><td>Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132SD_VFNMADD213SD_VFNMADD231SD.html">VFNMADD132SD</a></td><td>Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132SS_VFNMADD213SS_VFNMADD231SS.html">VFNMADD132SS</a></td><td>Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132PD_VFNMADD213PD_VFNMADD231PD.html">VFNMADD213PD</a></td><td>Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132PS_VFNMADD213PS_VFNMADD231PS.html">VFNMADD213PS</a></td><td>Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132SD_VFNMADD213SD_VFNMADD231SD.html">VFNMADD213SD</a></td><td>Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132SS_VFNMADD213SS_VFNMADD231SS.html">VFNMADD213SS</a></td><td>Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132PD_VFNMADD213PD_VFNMADD231PD.html">VFNMADD231PD</a></td><td>Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132PS_VFNMADD213PS_VFNMADD231PS.html">VFNMADD231PS</a></td><td>Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132SD_VFNMADD213SD_VFNMADD231SD.html">VFNMADD231SD</a></td><td>Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMADD132SS_VFNMADD213SS_VFNMADD231SS.html">VFNMADD231SS</a></td><td>Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132PD_VFNMSUB213PD_VFNMSUB231PD.html">VFNMSUB132PD</a></td><td>Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132PS_VFNMSUB213PS_VFNMSUB231PS.html">VFNMSUB132PS</a></td><td>Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132SD_VFNMSUB213SD_VFNMSUB231SD.html">VFNMSUB132SD</a></td><td>Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132SS_VFNMSUB213SS_VFNMSUB231SS.html">VFNMSUB132SS</a></td><td>Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132PD_VFNMSUB213PD_VFNMSUB231PD.html">VFNMSUB213PD</a></td><td>Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132PS_VFNMSUB213PS_VFNMSUB231PS.html">VFNMSUB213PS</a></td><td>Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132SD_VFNMSUB213SD_VFNMSUB231SD.html">VFNMSUB213SD</a></td><td>Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132SS_VFNMSUB213SS_VFNMSUB231SS.html">VFNMSUB213SS</a></td><td>Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132PD_VFNMSUB213PD_VFNMSUB231PD.html">VFNMSUB231PD</a></td><td>Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132PS_VFNMSUB213PS_VFNMSUB231PS.html">VFNMSUB231PS</a></td><td>Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values</td><td>AVX512F, AVX512VL, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132SD_VFNMSUB213SD_VFNMSUB231SD.html">VFNMSUB231SD</a></td><td>Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFNMSUB132SS_VFNMSUB213SS_VFNMSUB231SS.html">VFNMSUB231SS</a></td><td>Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values</td><td>AVX512F, FMA</td></tr>
<tr><td><a href="./html/VFPCLASSPD.html">VFPCLASSPD</a></td><td>Tests Types Of a Packed Float64 Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VFPCLASSPS.html">VFPCLASSPS</a></td><td>Tests Types Of a Packed Float32 Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VFPCLASSSD.html">VFPCLASSSD</a></td><td>Tests Types Of a Scalar Float64 Values</td><td>AVX512DQ</td></tr>
<tr><td><a href="./html/VFPCLASSSS.html">VFPCLASSSS</a></td><td>Tests Types Of a Scalar Float32 Values</td><td>AVX512DQ</td></tr>
<tr><td><a href="./html/VGATHERDPS_VGATHERDPD.html">VGATHERDPD</a></td><td>Gather Packed Single, Packed Double with Signed Dword</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VGATHERDPS_VGATHERQPS.html">VGATHERDPS</a></td><td>Gather Packed SP FP values Using Signed Dword/Qword Indices</td><td>AVX2</td></tr>
<tr><td><a href="./html/VGATHERPF0DPS_VGATHERPF0QPS_VGATHERPF0DPD_VGATHERPF0QPD.html">VGATHERPF0DPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERPF0DPS_VGATHERPF0QPS_VGATHERPF0DPD_VGATHERPF0QPD.html">VGATHERPF0DPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERPF0DPS_VGATHERPF0QPS_VGATHERPF0DPD_VGATHERPF0QPD.html">VGATHERPF0QPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERPF0DPS_VGATHERPF0QPS_VGATHERPF0DPD_VGATHERPF0QPD.html">VGATHERPF0QPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERPF1DPS_VGATHERPF1QPS_VGATHERPF1DPD_VGATHERPF1QPD.html">VGATHERPF1DPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERPF1DPS_VGATHERPF1QPS_VGATHERPF1DPD_VGATHERPF1QPD.html">VGATHERPF1DPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERPF1DPS_VGATHERPF1QPS_VGATHERPF1DPD_VGATHERPF1QPD.html">VGATHERPF1QPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERPF1DPS_VGATHERPF1QPS_VGATHERPF1DPD_VGATHERPF1QPD.html">VGATHERPF1QPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VGATHERQPS_VGATHERQPD.html">VGATHERQPD</a></td><td>Gather Packed Single, Packed Double with Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VGATHERQPS_VGATHERQPD.html">VGATHERQPS</a></td><td>Gather Packed Single, Packed Double with Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VGETEXPPD.html">VGETEXPPD</a></td><td>Convert Exponents of Packed DP FP Values to DP FP Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VGETEXPPS.html">VGETEXPPS</a></td><td>Convert Exponents of Packed SP FP Values to SP FP Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VGETEXPSD.html">VGETEXPSD</a></td><td>Convert Exponents of Scalar DP FP Values to DP FP Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VGETEXPSS.html">VGETEXPSS</a></td><td>Convert Exponents of Scalar SP FP Values to SP FP Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VGETMANTPD.html">VGETMANTPD</a></td><td>Extract Float64 Vector of Normalized Mantissas from Float64 Vector</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VGETMANTPS.html">VGETMANTPS</a></td><td>Extract Float32 Vector of Normalized Mantissas from Float32 Vector</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VGETMANTSD.html">VGETMANTSD</a></td><td>Extract Float64 of Normalized Mantissas from Float64 Scalar</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VGETMANTSS.html">VGETMANTSS</a></td><td>Extract Float32 Vector of Normalized Mantissa from Float32 Vector</td><td>AVX512F</td></tr>
<tr><td><a href="./html/HADDPD.html">VHADDPD</a></td><td>Packed Double-FP Horizontal Add</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/HADDPS.html">VHADDPS</a></td><td>Packed Single-FP Horizontal Add</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/HSUBPD.html">VHSUBPD</a></td><td>Packed Double-FP Horizontal Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/HSUBPS.html">VHSUBPS</a></td><td>Packed Single-FP Horizontal Subtract</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/VINSERTF128_VINSERTF32x4_VINSERTF64x2_VINSERTF32x8_VINSERTF64x4.html">VINSERTF128</a></td><td>Insert Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTF128_VINSERTF32x4_VINSERTF64x2_VINSERTF32x8_VINSERTF64x4.html">VINSERTF32x4</a></td><td>Insert Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTF128_VINSERTF32x4_VINSERTF64x2_VINSERTF32x8_VINSERTF64x4.html">VINSERTF32x8</a></td><td>Insert Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTF128_VINSERTF32x4_VINSERTF64x2_VINSERTF32x8_VINSERTF64x4.html">VINSERTF64x2</a></td><td>Insert Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTF128_VINSERTF32x4_VINSERTF64x2_VINSERTF32x8_VINSERTF64x4.html">VINSERTF64x4</a></td><td>Insert Packed Floating-Point Values</td><td>AVX, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTI128_VINSERTI32x4_VINSERTI64x2_VINSERTI32x8_VINSERTI64x4.html">VINSERTI128</a></td><td>Insert Packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTI128_VINSERTI32x4_VINSERTI64x2_VINSERTI32x8_VINSERTI64x4.html">VINSERTI32x4</a></td><td>Insert Packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTI128_VINSERTI32x4_VINSERTI64x2_VINSERTI32x8_VINSERTI64x4.html">VINSERTI32x8</a></td><td>Insert Packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTI128_VINSERTI32x4_VINSERTI64x2_VINSERTI32x8_VINSERTI64x4.html">VINSERTI64x2</a></td><td>Insert Packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VINSERTI128_VINSERTI32x4_VINSERTI64x2_VINSERTI32x8_VINSERTI64x4.html">VINSERTI64x4</a></td><td>Insert Packed Integer Values</td><td>AVX2, AVX512DQ, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/INSERTPS.html">VINSERTPS</a></td><td>Insert Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE4_1</td></tr>
<tr><td><a href="./html/LDDQU.html">VLDDQU</a></td><td>Load Unaligned Integer 128 Bits</td><td>AVX, SSE3</td></tr>
<tr><td><a href="./html/LDMXCSR.html">VLDMXCSR</a></td><td>Load MXCSR Register</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/MASKMOVDQU.html">VMASKMOVDQU</a></td><td>Store Selected Bytes of Double Quadword</td><td>AVX, SSE2</td></tr>
<tr><td><a href="./html/VMASKMOV.html">VMASKMOVPD</a></td><td>Conditional SIMD Packed Loads and Stores</td><td>AVX</td></tr>
<tr><td><a href="./html/VMASKMOV.html">VMASKMOVPS</a></td><td>Conditional SIMD Packed Loads and Stores</td><td>AVX</td></tr>
<tr><td><a href="./html/MAXPD.html">VMAXPD</a></td><td>Maximum of Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MAXPS.html">VMAXPS</a></td><td>Maximum of Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MAXSD.html">VMAXSD</a></td><td>Return Maximum Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MAXSS.html">VMAXSS</a></td><td>Return Maximum Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MINPD.html">VMINPD</a></td><td>Minimum of Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MINPS.html">VMINPS</a></td><td>Minimum of Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MINSD.html">VMINSD</a></td><td>Return Minimum Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MINSS.html">VMINSS</a></td><td>Return Minimum Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVAPD.html">VMOVAPD</a></td><td>Move Aligned Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVAPS.html">VMOVAPS</a></td><td>Move Aligned Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MOVD_MOVQ.html">VMOVD</a></td><td>Move Doubleword/Move Quadword</td><td>AVX, AVX512F, MMX, SSE2</td></tr>
<tr><td><a href="./html/MOVDDUP.html">VMOVDDUP</a></td><td>Replicate Double FP Values</td><td>AVX, AVX512F, AVX512VL, SSE3</td></tr>
<tr><td><a href="./html/MOVDQA,VMOVDQA32_64.html">VMOVDQA</a></td><td>Move Aligned Packed Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQA,VMOVDQA32_64.html">VMOVDQA32</a></td><td>Move Aligned Packed Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQA,VMOVDQA32_64.html">VMOVDQA64</a></td><td>Move Aligned Packed Integer Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQU,VMOVDQU8_16_32_64.html">VMOVDQU</a></td><td>Move Unaligned Packed Integer Values</td><td>AVX, AVX512BW, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQU,VMOVDQU8_16_32_64.html">VMOVDQU16</a></td><td>Move Unaligned Packed Integer Values</td><td>AVX, AVX512BW, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQU,VMOVDQU8_16_32_64.html">VMOVDQU32</a></td><td>Move Unaligned Packed Integer Values</td><td>AVX, AVX512BW, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQU,VMOVDQU8_16_32_64.html">VMOVDQU64</a></td><td>Move Unaligned Packed Integer Values</td><td>AVX, AVX512BW, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVDQU,VMOVDQU8_16_32_64.html">VMOVDQU8</a></td><td>Move Unaligned Packed Integer Values</td><td>AVX, AVX512BW, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVHLPS.html">VMOVHLPS</a></td><td>Move Packed Single-Precision Floating-Point Values High to Low</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVHPD.html">VMOVHPD</a></td><td>Move High Packed Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MOVHPS.html">VMOVHPS</a></td><td>Move High Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVLHPS.html">VMOVLHPS</a></td><td>Move Packed Single-Precision Floating-Point Values Low to High</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVLPD.html">VMOVLPD</a></td><td>Move Low Packed Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MOVLPS.html">VMOVLPS</a></td><td>Move Low Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVMSKPD.html">VMOVMSKPD</a></td><td>Extract Packed Double-Precision Floating-Point Sign Mask</td><td>AVX, SSE2</td></tr>
<tr><td><a href="./html/MOVMSKPS.html">VMOVMSKPS</a></td><td>Extract Packed Single-Precision Floating-Point Sign Mask</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/MOVNTDQ.html">VMOVNTDQ</a></td><td>Store Packed Integers Using Non-Temporal Hint</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVNTDQA.html">VMOVNTDQA</a></td><td>Load Double Quadword Non-Temporal Aligned Hint</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/MOVNTPD.html">VMOVNTPD</a></td><td>Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVNTPS.html">VMOVNTPS</a></td><td>Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MOVQ.html">VMOVQ</a></td><td>Move Quadword</td><td>AVX, AVX512F, MMX, SSE2</td></tr>
<tr><td><a href="./html/MOVSD.html">VMOVSD</a></td><td>Move or Merge Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MOVSHDUP.html">VMOVSHDUP</a></td><td>Replicate Single FP Values</td><td>AVX, AVX512F, AVX512VL, SSE3</td></tr>
<tr><td><a href="./html/MOVSLDUP.html">VMOVSLDUP</a></td><td>Replicate Single FP Values</td><td>AVX, AVX512F, AVX512VL, SSE3</td></tr>
<tr><td><a href="./html/MOVSS.html">VMOVSS</a></td><td>Move or Merge Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/MOVUPD.html">VMOVUPD</a></td><td>Move Unaligned Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MOVUPS.html">VMOVUPS</a></td><td>Move Unaligned Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MPSADBW.html">VMPSADBW</a></td><td>Compute Multiple Packed Sums of Absolute Difference</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/MULPD.html">VMULPD</a></td><td>Multiply Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/MULPS.html">VMULPS</a></td><td>Multiply Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/MULSD.html">VMULSD</a></td><td>Multiply Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/MULSS.html">VMULSS</a></td><td>Multiply Scalar Single-Precision Floating-Point Values</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/ORPD.html">VORPD</a></td><td>Bitwise Logical OR of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/ORPS.html">VORPS</a></td><td>Bitwise Logical OR of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">VPABSB</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">VPABSD</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">VPABSQ</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PABSB_PABSW_PABSD_PABSQ.html">VPABSW</a></td><td>Packed Absolute Value</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PACKSSWB_PACKSSDW.html">VPACKSSDW</a></td><td>Pack with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PACKSSWB_PACKSSDW.html">VPACKSSWB</a></td><td>Pack with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PACKUSDW.html">VPACKUSDW</a></td><td>Pack with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PACKUSWB.html">VPACKUSWB</a></td><td>Pack with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">VPADDB</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">VPADDD</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">VPADDQ</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDSB_PADDSW.html">VPADDSB</a></td><td>Add Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDSB_PADDSW.html">VPADDSW</a></td><td>Add Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDUSB_PADDUSW.html">VPADDUSB</a></td><td>Add Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDUSB_PADDUSW.html">VPADDUSW</a></td><td>Add Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PADDB_PADDW_PADDD_PADDQ.html">VPADDW</a></td><td>Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PALIGNR.html">VPALIGNR</a></td><td>Packed Align Right</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PAND.html">VPAND</a></td><td>Logical AND</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PAND.html">VPANDD</a></td><td>Logical AND</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PANDN.html">VPANDN</a></td><td>Logical AND NOT</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PANDN.html">VPANDND</a></td><td>Logical AND NOT</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PANDN.html">VPANDNQ</a></td><td>Logical AND NOT</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PAND.html">VPANDQ</a></td><td>Logical AND</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PAVGB_PAVGW.html">VPAVGB</a></td><td>Average Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/PAVGB_PAVGW.html">VPAVGW</a></td><td>Average Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/VPBLENDD.html">VPBLENDD</a></td><td>Blend Packed Dwords</td><td>AVX2</td></tr>
<tr><td><a href="./html/VPBLENDMB_VPBLENDMW.html">VPBLENDMB</a></td><td>Blend Byte/Word Vectors Using an Opmask Control</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/VPBLENDMD_VPBLENDMQ.html">VPBLENDMD</a></td><td>Blend Int32/Int64 Vectors Using an OpMask Control</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBLENDMD_VPBLENDMQ.html">VPBLENDMQ</a></td><td>Blend Int32/Int64 Vectors Using an OpMask Control</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBLENDMB_VPBLENDMW.html">VPBLENDMW</a></td><td>Blend Byte/Word Vectors Using an Opmask Control</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/PBLENDVB.html">VPBLENDVB</a></td><td>Variable Blend Packed Bytes</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PBLENDW.html">VPBLENDW</a></td><td>Blend Packed Words</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/VPBROADCASTB_W_D_Q.html">VPBROADCASTB</a></td><td>Load with Broadcast Integer Data from General Purpose Register</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCASTB_W_D_Q.html">VPBROADCASTD</a></td><td>Load with Broadcast Integer Data from General Purpose Register</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCASTM.html">VPBROADCASTMB2Q</a></td><td>Broadcast Mask to Vector Register</td><td>AVX512CD, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCASTM.html">VPBROADCASTMW2D</a></td><td>Broadcast Mask to Vector Register</td><td>AVX512CD, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCASTB_W_D_Q.html">VPBROADCASTQ</a></td><td>Load with Broadcast Integer Data from General Purpose Register</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPBROADCASTB_W_D_Q.html">VPBROADCASTW</a></td><td>Load with Broadcast Integer Data from General Purpose Register</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PCLMULQDQ.html">VPCLMULQDQ</a></td><td>PCLMULQDQ - Carry-Less Multiplication Quadword </td><td>AVX, PCLMULQDQ</td></tr>
<tr><td><a href="./html/VPCMPB_VPCMPUB.html">VPCMPB</a></td><td>Compare Packed Byte Values Into Mask</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/VPCMPD_VPCMPUD.html">VPCMPD</a></td><td>Compare Packed Integer Values into Mask</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PCMPEQB_PCMPEQW_PCMPEQD.html">VPCMPEQB</a></td><td>Compare Packed Data for Equal</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPEQB_PCMPEQW_PCMPEQD.html">VPCMPEQD</a></td><td>Compare Packed Data for Equal</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPEQQ.html">VPCMPEQQ</a></td><td>Compare Packed Qword Data for Equal</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PCMPEQB_PCMPEQW_PCMPEQD.html">VPCMPEQW</a></td><td>Compare Packed Data for Equal</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPESTRI.html">VPCMPESTRI</a></td><td>Packed Compare Explicit Length Strings, Return Index</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPESTRM.html">VPCMPESTRM</a></td><td>Packed Compare Explicit Length Strings, Return Mask</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPGTB_PCMPGTW_PCMPGTD.html">VPCMPGTB</a></td><td>Compare Packed Signed Integers for Greater Than</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPGTB_PCMPGTW_PCMPGTD.html">VPCMPGTD</a></td><td>Compare Packed Signed Integers for Greater Than</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPGTQ.html">VPCMPGTQ</a></td><td>Compare Packed Data for Greater Than</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPGTB_PCMPGTW_PCMPGTD.html">VPCMPGTW</a></td><td>Compare Packed Signed Integers for Greater Than</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PCMPISTRI.html">VPCMPISTRI</a></td><td>Packed Compare Implicit Length Strings, Return Index</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/PCMPISTRM.html">VPCMPISTRM</a></td><td>Packed Compare Implicit Length Strings, Return Mask</td><td>AVX, SSE4_2</td></tr>
<tr><td><a href="./html/VPCMPQ_VPCMPUQ.html">VPCMPQ</a></td><td>Compare Packed Integer Values into Mask</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPCMPB_VPCMPUB.html">VPCMPUB</a></td><td>Compare Packed Byte Values Into Mask</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/VPCMPD_VPCMPUD.html">VPCMPUD</a></td><td>Compare Packed Integer Values into Mask</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPCMPQ_VPCMPUQ.html">VPCMPUQ</a></td><td>Compare Packed Integer Values into Mask</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPCMPW_VPCMPUW.html">VPCMPUW</a></td><td>Compare Packed Word Values Into Mask</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/VPCMPW_VPCMPUW.html">VPCMPW</a></td><td>Compare Packed Word Values Into Mask</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/VPCOMPRESSD.html">VPCOMPRESSD</a></td><td>Store Sparse Packed Doubleword Integer Values into Dense Memory/Register</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPCOMPRESSQ.html">VPCOMPRESSQ</a></td><td>Store Sparse Packed Quadword Integer Values into Dense Memory/Register</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPCONFLICTD_Q.html">VPCONFLICTD</a></td><td>Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register</td><td>AVX512CD, AVX512VL</td></tr>
<tr><td><a href="./html/VPCONFLICTD_Q.html">VPCONFLICTQ</a></td><td>Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense Memory/ Register</td><td>AVX512CD, AVX512VL</td></tr>
<tr><td><a href="./html/VPERM2F128.html">VPERM2F128</a></td><td>Permute Floating-Point Values</td><td>AVX</td></tr>
<tr><td><a href="./html/VPERM2I128.html">VPERM2I128</a></td><td>Permute Integer Values</td><td>AVX2</td></tr>
<tr><td><a href="./html/VPERMD_VPERMW.html">VPERMD</a></td><td>Permute Packed Doublewords/Words Elements</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMI2W_D_Q_PS_PD.html">VPERMI2D</a></td><td>Full Permute From Two Tables Overwriting the Index</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMI2W_D_Q_PS_PD.html">VPERMI2PD</a></td><td>Full Permute From Two Tables Overwriting the Index</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMI2W_D_Q_PS_PD.html">VPERMI2PS</a></td><td>Full Permute From Two Tables Overwriting the Index</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMI2W_D_Q_PS_PD.html">VPERMI2Q</a></td><td>Full Permute From Two Tables Overwriting the Index</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMI2W_D_Q_PS_PD.html">VPERMI2W</a></td><td>Full Permute From Two Tables Overwriting the Index</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMILPD.html">VPERMILPD</a></td><td>Permute In-Lane of Pairs of Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMILPS.html">VPERMILPS</a></td><td>Permute In-Lane of Quadruples of Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMPD.html">VPERMPD</a></td><td>Permute Double-Precision Floating-Point Elements</td><td>AVX2, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMPS.html">VPERMPS</a></td><td>Permute Single-Precision Floating-Point Elements</td><td>AVX2, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMQ.html">VPERMQ</a></td><td>Qwords Element Permutation</td><td>AVX2, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPERMD_VPERMW.html">VPERMW</a></td><td>Permute Packed Doublewords/Words Elements</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPEXPANDD.html">VPEXPANDD</a></td><td>Load Sparse Packed Doubleword Integer Values from Dense Memory / Register</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPEXPANDQ.html">VPEXPANDQ</a></td><td>Load Sparse Packed Quadword Integer Values from Dense Memory / Register</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PEXTRB_PEXTRD_PEXTRQ.html">VPEXTRB</a></td><td>Extract Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PEXTRB_PEXTRD_PEXTRQ.html">VPEXTRD</a></td><td>Extract Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PEXTRB_PEXTRD_PEXTRQ.html">VPEXTRQ</a></td><td>Extract Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PEXTRW.html">VPEXTRW</a></td><td>Extract Word</td><td>AVX, AVX512BW, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/VPGATHERDD_VPGATHERQD.html">VPGATHERDD</a></td><td>Gather Packed Dword Values Using Signed Dword/Qword Indices</td><td>AVX2</td></tr>
<tr><td><a href="./html/VPGATHERDQ_VPGATHERQQ.html">VPGATHERDQ</a></td><td>Gather Packed Qword Values Using Signed Dword/Qword Indices</td><td>AVX2</td></tr>
<tr><td><a href="./html/VPGATHERQD_VPGATHERQQ.html">VPGATHERQD</a></td><td>Gather Packed Dword, Packed Qword with Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPGATHERQD_VPGATHERQQ.html">VPGATHERQQ</a></td><td>Gather Packed Dword, Packed Qword with Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PHADDW_PHADDD.html">VPHADDD</a></td><td>Packed Horizontal Add</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHADDSW.html">VPHADDSW</a></td><td>Packed Horizontal Add and Saturate</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHADDW_PHADDD.html">VPHADDW</a></td><td>Packed Horizontal Add</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHMINPOSUW.html">VPHMINPOSUW</a></td><td>Packed Horizontal Word Minimum</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/PHSUBW_PHSUBD.html">VPHSUBD</a></td><td>Packed Horizontal Subtract</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHSUBSW.html">VPHSUBSW</a></td><td>Packed Horizontal Subtract and Saturate</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PHSUBW_PHSUBD.html">VPHSUBW</a></td><td>Packed Horizontal Subtract</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PINSRB_PINSRD_PINSRQ.html">VPINSRB</a></td><td>Insert Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PINSRB_PINSRD_PINSRQ.html">VPINSRD</a></td><td>Insert Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PINSRB_PINSRD_PINSRQ.html">VPINSRQ</a></td><td>Insert Byte/Dword/Qword</td><td>AVX, AVX512BW, AVX512DQ, SSE4_1</td></tr>
<tr><td><a href="./html/PINSRW.html">VPINSRW</a></td><td>Insert Word</td><td>AVX, AVX512BW, SSE, SSE2</td></tr>
<tr><td><a href="./html/VPLZCNTD_Q.html">VPLZCNTD</a></td><td>Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values</td><td>AVX512CD, AVX512VL</td></tr>
<tr><td><a href="./html/VPLZCNTD_Q.html">VPLZCNTQ</a></td><td>Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values</td><td>AVX512CD, AVX512VL</td></tr>
<tr><td><a href="./html/PMADDUBSW.html">VPMADDUBSW</a></td><td>Multiply and Add Packed Signed and Unsigned Bytes</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PMADDWD.html">VPMADDWD</a></td><td>Multiply and Add Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/VPMASKMOV.html">VPMASKMOVD</a></td><td>Conditional SIMD Integer Packed Loads and Stores</td><td>AVX2</td></tr>
<tr><td><a href="./html/VPMASKMOV.html">VPMASKMOVQ</a></td><td>Conditional SIMD Integer Packed Loads and Stores</td><td>AVX2</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">VPMAXSB</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">VPMAXSD</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">VPMAXSQ</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXSB_PMAXSW_PMAXSD_PMAXSQ.html">VPMAXSW</a></td><td>Maximum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUB_PMAXUW.html">VPMAXUB</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUD_PMAXUQ.html">VPMAXUD</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUD_PMAXUQ.html">VPMAXUQ</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMAXUB_PMAXUW.html">VPMAXUW</a></td><td>Maximum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSB_PMINSW.html">VPMINSB</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSD_PMINSQ.html">VPMINSD</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSD_PMINSQ.html">VPMINSQ</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINSB_PMINSW.html">VPMINSW</a></td><td>Minimum of Packed Signed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUB_PMINUW.html">VPMINUB</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUD_PMINUQ.html">VPMINUD</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUD_PMINUQ.html">VPMINUQ</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMINUB_PMINUW.html">VPMINUW</a></td><td>Minimum of Packed Unsigned Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2, SSE4_1</td></tr>
<tr><td><a href="./html/VPMOVB2M_VPMOVW2M_VPMOVD2M_VPMOVQ2M.html">VPMOVB2M</a></td><td>Convert a Vector Register to a Mask</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVB2M_VPMOVW2M_VPMOVD2M_VPMOVQ2M.html">VPMOVD2M</a></td><td>Convert a Vector Register to a Mask</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVDB_VPMOVSDB_VPMOVUSDB.html">VPMOVDB</a></td><td>Down Convert DWord to Byte</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVDW_VPMOVSDW_VPMOVUSDW.html">VPMOVDW</a></td><td>Down Convert DWord to Word</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVM2B_VPMOVM2W_VPMOVM2D_VPMOVM2Q.html">VPMOVM2B</a></td><td>Convert a Mask Register to a Vector Register</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVM2B_VPMOVM2W_VPMOVM2D_VPMOVM2Q.html">VPMOVM2D</a></td><td>Convert a Mask Register to a Vector Register</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVM2B_VPMOVM2W_VPMOVM2D_VPMOVM2Q.html">VPMOVM2Q</a></td><td>Convert a Mask Register to a Vector Register</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVM2B_VPMOVM2W_VPMOVM2D_VPMOVM2Q.html">VPMOVM2W</a></td><td>Convert a Mask Register to a Vector Register</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/PMOVMSKB.html">VPMOVMSKB</a></td><td>Move Byte Mask</td><td>AVX, AVX2, SSE, SSE2</td></tr>
<tr><td><a href="./html/VPMOVB2M_VPMOVW2M_VPMOVD2M_VPMOVQ2M.html">VPMOVQ2M</a></td><td>Convert a Vector Register to a Mask</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQB_VPMOVSQB_VPMOVUSQB.html">VPMOVQB</a></td><td>Down Convert QWord to Byte</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQD_VPMOVSQD_VPMOVUSQD.html">VPMOVQD</a></td><td>Down Convert QWord to DWord</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQW_VPMOVSQW_VPMOVUSQW.html">VPMOVQW</a></td><td>Down Convert QWord to Word</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVDB_VPMOVSDB_VPMOVUSDB.html">VPMOVSDB</a></td><td>Down Convert DWord to Byte</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVDW_VPMOVSDW_VPMOVUSDW.html">VPMOVSDW</a></td><td>Down Convert DWord to Word</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQB_VPMOVSQB_VPMOVUSQB.html">VPMOVSQB</a></td><td>Down Convert QWord to Byte</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQD_VPMOVSQD_VPMOVUSQD.html">VPMOVSQD</a></td><td>Down Convert QWord to DWord</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQW_VPMOVSQW_VPMOVUSQW.html">VPMOVSQW</a></td><td>Down Convert QWord to Word</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVWB_VPMOVSWB_VPMOVUSWB.html">VPMOVSWB</a></td><td>Down Convert Word to Byte</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/PMOVSX.html">VPMOVSXBD</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">VPMOVSXBQ</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">VPMOVSXBW</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">VPMOVSXDQ</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">VPMOVSXWD</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVSX.html">VPMOVSXWQ</a></td><td>Packed Move with Sign Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/VPMOVDB_VPMOVSDB_VPMOVUSDB.html">VPMOVUSDB</a></td><td>Down Convert DWord to Byte</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVDW_VPMOVSDW_VPMOVUSDW.html">VPMOVUSDW</a></td><td>Down Convert DWord to Word</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQB_VPMOVSQB_VPMOVUSQB.html">VPMOVUSQB</a></td><td>Down Convert QWord to Byte</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQD_VPMOVSQD_VPMOVUSQD.html">VPMOVUSQD</a></td><td>Down Convert QWord to DWord</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVQW_VPMOVSQW_VPMOVUSQW.html">VPMOVUSQW</a></td><td>Down Convert QWord to Word</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVWB_VPMOVSWB_VPMOVUSWB.html">VPMOVUSWB</a></td><td>Down Convert Word to Byte</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVB2M_VPMOVW2M_VPMOVD2M_VPMOVQ2M.html">VPMOVW2M</a></td><td>Convert a Vector Register to a Mask</td><td>AVX512BW, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VPMOVWB_VPMOVSWB_VPMOVUSWB.html">VPMOVWB</a></td><td>Down Convert Word to Byte</td><td>AVX512BW, AVX512VL</td></tr>
<tr><td><a href="./html/PMOVZX.html">VPMOVZXBD</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">VPMOVZXBQ</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">VPMOVZXBW</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">VPMOVZXDQ</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">VPMOVZXWD</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMOVZX.html">VPMOVZXWQ</a></td><td>Packed Move with Zero Extend</td><td>AVX, AVX2, SSE4_1</td></tr>
<tr><td><a href="./html/PMULDQ.html">VPMULDQ</a></td><td>Multiply Packed Doubleword Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMULHRSW.html">VPMULHRSW</a></td><td>Packed Multiply High with Round and Scale</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PMULHUW.html">VPMULHUW</a></td><td>Multiply Packed Unsigned Integers and Store High Result</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/PMULHW.html">VPMULHW</a></td><td>Multiply Packed Signed Integers and Store High Result</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PMULLD_PMULLQ.html">VPMULLD</a></td><td>Multiply Packed Integers and Store Low Result</td><td>AVX, AVX2, AVX512DQ, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMULLD_PMULLQ.html">VPMULLQ</a></td><td>Multiply Packed Integers and Store Low Result</td><td>AVX, AVX2, AVX512DQ, AVX512F, AVX512VL, SSE4_1</td></tr>
<tr><td><a href="./html/PMULLW.html">VPMULLW</a></td><td>Multiply Packed Signed Integers and Store Low Result</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PMULUDQ.html">VPMULUDQ</a></td><td>Multiply Packed Unsigned Doubleword Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/POR.html">VPOR</a></td><td>Bitwise Logical OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/POR.html">VPORD</a></td><td>Bitwise Logical OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/POR.html">VPORQ</a></td><td>Bitwise Logical OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">VPROLD</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">VPROLQ</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">VPROLVD</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PROLD_PROLVD_PROLQ_PROLVQ.html">VPROLVQ</a></td><td>Bit Rotate Left</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">VPRORD</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">VPRORQ</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">VPRORVD</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PRORD_PRORVD_PRORQ_PRORVQ.html">VPRORVQ</a></td><td>Bit Rotate  Right</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PSADBW.html">VPSADBW</a></td><td>Compute Sum of Absolute Differences</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE, SSE2</td></tr>
<tr><td><a href="./html/VPSCATTERDD_VPSCATTERDQ_VPSCATTERQD_VPSCATTERQQ.html">VPSCATTERDD</a></td><td>Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSCATTERDD_VPSCATTERDQ_VPSCATTERQD_VPSCATTERQQ.html">VPSCATTERDQ</a></td><td>Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSCATTERDD_VPSCATTERDQ_VPSCATTERQD_VPSCATTERQQ.html">VPSCATTERQD</a></td><td>Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSCATTERDD_VPSCATTERDQ_VPSCATTERQD_VPSCATTERQQ.html">VPSCATTERQQ</a></td><td>Scatter Packed Dword, Packed Qword with Signed Dword, Signed Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PSHUFB.html">VPSHUFB</a></td><td>Packed Shuffle Bytes</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSSE3</td></tr>
<tr><td><a href="./html/PSHUFD.html">VPSHUFD</a></td><td>Shuffle Packed Doublewords</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSHUFHW.html">VPSHUFHW</a></td><td>Shuffle Packed High Words</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSHUFLW.html">VPSHUFLW</a></td><td>Shuffle Packed Low Words</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSIGNB_PSIGNW_PSIGND.html">VPSIGNB</a></td><td>Packed SIGN</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PSIGNB_PSIGNW_PSIGND.html">VPSIGND</a></td><td>Packed SIGN</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PSIGNB_PSIGNW_PSIGND.html">VPSIGNW</a></td><td>Packed SIGN</td><td>AVX, AVX2, SSSE3</td></tr>
<tr><td><a href="./html/PSLLW_PSLLD_PSLLQ.html">VPSLLD</a></td><td>Shift Packed Data Left Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSLLDQ.html">VPSLLDQ</a></td><td>Shift Double Quadword Left Logical</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSLLW_PSLLD_PSLLQ.html">VPSLLQ</a></td><td>Shift Packed Data Left Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/VPSLLVW_VPSLLVD_VPSLLVQ.html">VPSLLVD</a></td><td>Variable Bit Shift Left Logical</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSLLVW_VPSLLVD_VPSLLVQ.html">VPSLLVQ</a></td><td>Variable Bit Shift Left Logical</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSLLVW_VPSLLVD_VPSLLVQ.html">VPSLLVW</a></td><td>Variable Bit Shift Left Logical</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PSLLW_PSLLD_PSLLQ.html">VPSLLW</a></td><td>Shift Packed Data Left Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRAW_PSRAD_PSRAQ.html">VPSRAD</a></td><td>Shift Packed Data Right Arithmetic</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRAW_PSRAD_PSRAQ.html">VPSRAQ</a></td><td>Shift Packed Data Right Arithmetic</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/VPSRAVW_VPSRAVD_VPSRAVQ.html">VPSRAVD</a></td><td>Variable Bit Shift Right Arithmetic</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSRAVW_VPSRAVD_VPSRAVQ.html">VPSRAVQ</a></td><td>Variable Bit Shift Right Arithmetic</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSRAVW_VPSRAVD_VPSRAVQ.html">VPSRAVW</a></td><td>Variable Bit Shift Right Arithmetic</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PSRAW_PSRAD_PSRAQ.html">VPSRAW</a></td><td>Shift Packed Data Right Arithmetic</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRLW_PSRLD_PSRLQ.html">VPSRLD</a></td><td>Shift Packed Data Right Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSRLDQ.html">VPSRLDQ</a></td><td>Shift Double Quadword Right Logical</td><td>AVX, AVX2, AVX512BW, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSRLW_PSRLD_PSRLQ.html">VPSRLQ</a></td><td>Shift Packed Data Right Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/VPSRLVW_VPSRLVD_VPSRLVQ.html">VPSRLVD</a></td><td>Variable Bit Shift Right Logical</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSRLVW_VPSRLVD_VPSRLVQ.html">VPSRLVQ</a></td><td>Variable Bit Shift Right Logical</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPSRLVW_VPSRLVD_VPSRLVQ.html">VPSRLVW</a></td><td>Variable Bit Shift Right Logical</td><td>AVX2, AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PSRLW_PSRLD_PSRLQ.html">VPSRLW</a></td><td>Shift Packed Data Right Logical</td><td>AVX, AVX2, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBB_PSUBW_PSUBD.html">VPSUBB</a></td><td>Subtract Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBB_PSUBW_PSUBD.html">VPSUBD</a></td><td>Subtract Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBQ.html">VPSUBQ</a></td><td>Subtract Packed Quadword Integers</td><td>AVX, AVX2, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/PSUBSB_PSUBSW.html">VPSUBSB</a></td><td>Subtract Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBSB_PSUBSW.html">VPSUBSW</a></td><td>Subtract Packed Signed Integers with Signed Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBUSB_PSUBUSW.html">VPSUBUSB</a></td><td>Subtract Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBUSB_PSUBUSW.html">VPSUBUSW</a></td><td>Subtract Packed Unsigned Integers with Unsigned Saturation</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PSUBB_PSUBW_PSUBD.html">VPSUBW</a></td><td>Subtract Packed Integers</td><td>AVX, AVX2, AVX512BW, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/VPTERNLOGD_VPTERNLOGQ.html">VPTERNLOGD</a></td><td>Bitwise Ternary Logic</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTERNLOGD_VPTERNLOGQ.html">VPTERNLOGQ</a></td><td>Bitwise Ternary Logic</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PTEST.html">VPTEST</a></td><td>PTEST- Logical Compare </td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/VPTESTMB_VPTESTMW_VPTESTMD_VPTESTMQ.html">VPTESTMB</a></td><td>Logical AND and Set Mask</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTESTMB_VPTESTMW_VPTESTMD_VPTESTMQ.html">VPTESTMD</a></td><td>Logical AND and Set Mask</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTESTMB_VPTESTMW_VPTESTMD_VPTESTMQ.html">VPTESTMQ</a></td><td>Logical AND and Set Mask</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTESTMB_VPTESTMW_VPTESTMD_VPTESTMQ.html">VPTESTMW</a></td><td>Logical AND and Set Mask</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTESTNMB_W_D_Q.html">VPTESTNMB</a></td><td>Logical NAND and Set</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTESTNMB_W_D_Q.html">VPTESTNMD</a></td><td>Logical NAND and Set</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTESTNMB_W_D_Q.html">VPTESTNMQ</a></td><td>Logical NAND and Set</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VPTESTNMB_W_D_Q.html">VPTESTNMW</a></td><td>Logical NAND and Set</td><td>AVX512BW, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">VPUNPCKHBW</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">VPUNPCKHDQ</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">VPUNPCKHQDQ</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKHBW_PUNPCKHWD_PUNPCKHDQ_PUNPCKHQDQ.html">VPUNPCKHWD</a></td><td>Unpack High Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">VPUNPCKLBW</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">VPUNPCKLDQ</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">VPUNPCKLQDQ</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PUNPCKLBW_PUNPCKLWD_PUNPCKLDQ_PUNPCKLQDQ.html">VPUNPCKLWD</a></td><td>Unpack Low Data</td><td>AVX, AVX2, AVX512BW, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PXOR.html">VPXOR</a></td><td>Logical Exclusive OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PXOR.html">VPXORD</a></td><td>Logical Exclusive OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/PXOR.html">VPXORQ</a></td><td>Logical Exclusive OR</td><td>AVX, AVX2, AVX512F, AVX512VL, MMX, SSE2</td></tr>
<tr><td><a href="./html/VRANGEPD.html">VRANGEPD</a></td><td>Range Restriction Calculation For Packed Pairs of Float64 Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VRANGEPS.html">VRANGEPS</a></td><td>Range Restriction Calculation For Packed Pairs of Float32 Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VRANGESD.html">VRANGESD</a></td><td>Range Restriction Calculation From a pair of Scalar Float64 Values</td><td>AVX512DQ</td></tr>
<tr><td><a href="./html/VRANGESS.html">VRANGESS</a></td><td>Range Restriction Calculation From a Pair of Scalar Float32 Values</td><td>AVX512DQ</td></tr>
<tr><td><a href="./html/VRCP14PD.html">VRCP14PD</a></td><td>Compute Approximate Reciprocals of Packed Float64 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VRCP14PS.html">VRCP14PS</a></td><td>Compute Approximate Reciprocals of Packed Float32 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VRCP14SD.html">VRCP14SD</a></td><td>Compute Approximate Reciprocal of Scalar Float64 Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VRCP14SS.html">VRCP14SS</a></td><td>Compute Approximate Reciprocal of Scalar Float32 Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VRCP28PD.html">VRCP28PD</a></td><td>Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VRCP28PS.html">VRCP28PS</a></td><td>Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VRCP28SD.html">VRCP28SD</a></td><td>Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VRCP28SS.html">VRCP28SS</a></td><td>Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/RCPPS.html">VRCPPS</a></td><td>Compute Reciprocals of Packed Single-Precision Floating-Point Values</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/RCPSS.html">VRCPSS</a></td><td>Compute Reciprocal of Scalar Single-Precision Floating-Point Values</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/VREDUCEPD.html">VREDUCEPD</a></td><td>Perform Reduction Transformation on Packed Float64 Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VREDUCEPS.html">VREDUCEPS</a></td><td>Perform Reduction Transformation on Packed Float32 Values</td><td>AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/VREDUCESD.html">VREDUCESD</a></td><td>Perform a Reduction Transformation on a Scalar Float64 Value</td><td>AVX512DQ</td></tr>
<tr><td><a href="./html/VREDUCESS.html">VREDUCESS</a></td><td>Perform a Reduction Transformation on a Scalar Float32 Value</td><td>AVX512DQ</td></tr>
<tr><td><a href="./html/VRNDSCALEPD.html">VRNDSCALEPD</a></td><td>Round Packed Float64 Values To Include A Given Number Of Fraction Bits</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VRNDSCALEPS.html">VRNDSCALEPS</a></td><td>Round Packed Float32 Values To Include A Given Number Of Fraction Bits</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VRNDSCALESD.html">VRNDSCALESD</a></td><td>Round Scalar Float64 Value To Include A Given Number Of Fraction Bits</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VRNDSCALESS.html">VRNDSCALESS</a></td><td>Round Scalar Float32 Value To Include A Given Number Of Fraction Bits</td><td>AVX512F</td></tr>
<tr><td><a href="./html/ROUNDPD.html">VROUNDPD</a></td><td>Round Packed Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/ROUNDPS.html">VROUNDPS</a></td><td>Round Packed Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/ROUNDSD.html">VROUNDSD</a></td><td>Round Scalar Double Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/ROUNDSS.html">VROUNDSS</a></td><td>Round Scalar Single Precision Floating-Point Values</td><td>AVX, SSE4_1</td></tr>
<tr><td><a href="./html/VRSQRT14PD.html">VRSQRT14PD</a></td><td>Compute Approximate Reciprocals of Square Roots of Packed Float64 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VRSQRT14PS.html">VRSQRT14PS</a></td><td>Compute Approximate Reciprocals of Square Roots of Packed Float32 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VRSQRT14SD.html">VRSQRT14SD</a></td><td>Compute Approximate Reciprocal of Square Root of Scalar Float64 Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VRSQRT14SS.html">VRSQRT14SS</a></td><td>Compute Approximate Reciprocal of Square Root of Scalar Float32 Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VRSQRT28PD.html">VRSQRT28PD</a></td><td>Approximation to the Reciprocal Square Root of Packed Double-Precision Floating-Point Values with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VRSQRT28PS.html">VRSQRT28PS</a></td><td>Approximation to the Reciprocal Square Root of Packed Single-Precision Floating-Point Values with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VRSQRT28SD.html">VRSQRT28SD</a></td><td>Approximation to the Reciprocal Square Root of Scalar Double-Precision Floating-Point Value with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/VRSQRT28SS.html">VRSQRT28SS</a></td><td>Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-Point Value with Less Than 2^-28 Relative Error</td><td>AVX512ER</td></tr>
<tr><td><a href="./html/RSQRTPS.html">VRSQRTPS</a></td><td>Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/RSQRTSS.html">VRSQRTSS</a></td><td>Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/VSCALEFPD.html">VSCALEFPD</a></td><td>Scale Packed Float64 Values With Float64 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSCALEFPS.html">VSCALEFPS</a></td><td>Scale Packed Float32 Values With Float32 Values</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSCALEFSD.html">VSCALEFSD</a></td><td>Scale Scalar Float64 Values With Float64 Values</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VSCALEFSS.html">VSCALEFSS</a></td><td>Scale Scalar Float32 Value With Float32 Value</td><td>AVX512F</td></tr>
<tr><td><a href="./html/VSCATTERDPS_VSCATTERDPD_VSCATTERQPS_VSCATTERQPD.html">VSCATTERDPD</a></td><td>Scatter Packed Single, Packed Double with Signed Dword and Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSCATTERDPS_VSCATTERDPD_VSCATTERQPS_VSCATTERQPD.html">VSCATTERDPS</a></td><td>Scatter Packed Single, Packed Double with Signed Dword and Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSCATTERPF0DPS_VSCATTERPF0QPS_VSCATTERPF0DPD_VSCATTERPF0QPD.html">VSCATTERPF0DPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERPF0DPS_VSCATTERPF0QPS_VSCATTERPF0DPD_VSCATTERPF0QPD.html">VSCATTERPF0DPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERPF0DPS_VSCATTERPF0QPS_VSCATTERPF0DPD_VSCATTERPF0QPD.html">VSCATTERPF0QPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERPF0DPS_VSCATTERPF0QPS_VSCATTERPF0DPD_VSCATTERPF0QPD.html">VSCATTERPF0QPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERPF1DPS_VSCATTERPF1QPS_VSCATTERPF1DPD_VSCATTERPF1QPD.html">VSCATTERPF1DPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERPF1DPS_VSCATTERPF1QPS_VSCATTERPF1DPD_VSCATTERPF1QPD.html">VSCATTERPF1DPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERPF1DPS_VSCATTERPF1QPS_VSCATTERPF1DPD_VSCATTERPF1QPD.html">VSCATTERPF1QPD</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERPF1DPS_VSCATTERPF1QPS_VSCATTERPF1DPD_VSCATTERPF1QPD.html">VSCATTERPF1QPS</a></td><td>Sparse Prefetch Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent to Write</td><td>AVX512PF</td></tr>
<tr><td><a href="./html/VSCATTERDPS_VSCATTERDPD_VSCATTERQPS_VSCATTERQPD.html">VSCATTERQPD</a></td><td>Scatter Packed Single, Packed Double with Signed Dword and Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSCATTERDPS_VSCATTERDPD_VSCATTERQPS_VSCATTERQPD.html">VSCATTERQPS</a></td><td>Scatter Packed Single, Packed Double with Signed Dword and Qword Indices</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSHUFF32x4_VSHUFF64x2_VSHUFI32x4_VSHUFI64x2.html">VSHUFF32x4</a></td><td>Shuffle Packed Values at 128-bit Granularity</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSHUFF32x4_VSHUFF64x2_VSHUFI32x4_VSHUFI64x2.html">VSHUFF64x2</a></td><td>Shuffle Packed Values at 128-bit Granularity</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSHUFF32x4_VSHUFF64x2_VSHUFI32x4_VSHUFI64x2.html">VSHUFI32x4</a></td><td>Shuffle Packed Values at 128-bit Granularity</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/VSHUFF32x4_VSHUFF64x2_VSHUFI32x4_VSHUFI64x2.html">VSHUFI64x2</a></td><td>Shuffle Packed Values at 128-bit Granularity</td><td>AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/SHUFPD.html">VSHUFPD</a></td><td>Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/SHUFPS.html">VSHUFPS</a></td><td>Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/SQRTPD.html">VSQRTPD</a></td><td>Square Root of Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/SQRTPS.html">VSQRTPS</a></td><td>Square Root of Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/SQRTSD.html">VSQRTSD</a></td><td>Compute Square Root of Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/SQRTSS.html">VSQRTSS</a></td><td>Compute Square Root of Scalar Single-Precision Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/STMXCSR.html">VSTMXCSR</a></td><td>Store MXCSR Register State</td><td>AVX, SSE</td></tr>
<tr><td><a href="./html/SUBPD.html">VSUBPD</a></td><td>Subtract Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE2</td></tr>
<tr><td><a href="./html/SUBPS.html">VSUBPS</a></td><td>Subtract Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/SUBSD.html">VSUBSD</a></td><td>Subtract Scalar Double-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/SUBSS.html">VSUBSS</a></td><td>Subtract Scalar Single-Precision Floating-Point Value</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/VTESTPD_VTESTPS.html">VTESTPD</a></td><td>Packed Bit Test</td><td>AVX</td></tr>
<tr><td><a href="./html/VTESTPD_VTESTPS.html">VTESTPS</a></td><td>Packed Bit Test</td><td>AVX</td></tr>
<tr><td><a href="./html/UCOMISD.html">VUCOMISD</a></td><td>Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE2</td></tr>
<tr><td><a href="./html/UCOMISS.html">VUCOMISS</a></td><td>Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS</td><td>AVX, AVX512F, SSE</td></tr>
<tr><td><a href="./html/UNPCKHPD.html">VUNPCKHPD</a></td><td>Unpack and Interleave High Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/UNPCKHPS.html">VUNPCKHPS</a></td><td>Unpack and Interleave High Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/UNPCKLPD.html">VUNPCKLPD</a></td><td>Unpack and Interleave Low Packed Double-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/UNPCKLPS.html">VUNPCKLPS</a></td><td>Unpack and Interleave Low Packed Single-Precision Floating-Point Values</td><td>AVX, AVX512F, AVX512VL</td></tr>
<tr><td><a href="./html/XORPD.html">VXORPD</a></td><td>Bitwise Logical XOR of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/XORPS.html">VXORPS</a></td><td>Bitwise Logical XOR of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/VZEROALL.html">VZEROALL</a></td><td>Zero All YMM Registers</td><td>AVX</td></tr>
<tr><td><a href="./html/VZEROUPPER.html">VZEROUPPER</a></td><td>Zero Upper Bits of YMM Registers</td><td>AVX</td></tr>
<tr><td><a href="./html/WAIT_FWAIT.html">WAIT</a></td><td>Wait</td><td></td></tr>
<tr><td><a href="./html/WBINVD.html">WBINVD</a></td><td>Write Back and Invalidate Cache</td><td></td></tr>
<tr><td><a href="./html/WRFSBASE_WRGSBASE.html">WRFSBASE</a></td><td>Write FS/GS Segment Base</td><td>FSGSBASE</td></tr>
<tr><td><a href="./html/WRFSBASE_WRGSBASE.html">WRGSBASE</a></td><td>Write FS/GS Segment Base</td><td>FSGSBASE</td></tr>
<tr><td><a href="./html/WRMSR.html">WRMSR</a></td><td>Write to Model Specific Register</td><td></td></tr>
<tr><td><a href="./html/WRPKRU.html">WRPKRU</a></td><td>Write Data to User Page Key Register</td><td></td></tr>
<tr><td><a href="./html/XABORT.html">XABORT</a></td><td>Transactional Abort</td><td>RTM</td></tr>
<tr><td><a href="./html/XACQUIRE_XRELEASE.html">XACQUIRE</a></td><td>Hardware Lock Elision Prefix Hints</td><td>HLE</td></tr>
<tr><td><a href="./html/XADD.html">XADD</a></td><td>Exchange and Add</td><td></td></tr>
<tr><td><a href="./html/XBEGIN.html">XBEGIN</a></td><td>Transactional Begin</td><td>RTM</td></tr>
<tr><td><a href="./html/XCHG.html">XCHG</a></td><td>Exchange Register/Memory with Register</td><td></td></tr>
<tr><td><a href="./html/XEND.html">XEND</a></td><td>Transactional End</td><td>RTM</td></tr>
<tr><td><a href="./html/XGETBV.html">XGETBV</a></td><td>Get Value of Extended Control Register</td><td></td></tr>
<tr><td><a href="./html/XLAT_XLATB.html">XLAT</a></td><td>Table Look-up Translation</td><td></td></tr>
<tr><td><a href="./html/XLAT_XLATB.html">XLATB</a></td><td>Table Look-up Translation</td><td></td></tr>
<tr><td><a href="./html/XOR.html">XOR</a></td><td>Logical Exclusive OR</td><td></td></tr>
<tr><td><a href="./html/XORPD.html">XORPD</a></td><td>Bitwise Logical XOR of Packed Double Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL</td></tr>
<tr><td><a href="./html/XORPS.html">XORPS</a></td><td>Bitwise Logical XOR of Packed Single Precision Floating-Point Values</td><td>AVX, AVX512DQ, AVX512VL, SSE</td></tr>
<tr><td><a href="./html/XACQUIRE_XRELEASE.html">XRELEASE</a></td><td>Hardware Lock Elision Prefix Hints</td><td>HLE</td></tr>
<tr><td><a href="./html/XRSTOR.html">XRSTOR</a></td><td>Restore Processor Extended States</td><td></td></tr>
<tr><td><a href="./html/XRSTORS.html">XRSTORS</a></td><td>Restore Processor Extended States Supervisor</td><td></td></tr>
<tr><td><a href="./html/XSAVE.html">XSAVE</a></td><td>Save Processor Extended States</td><td></td></tr>
<tr><td><a href="./html/XSAVEC.html">XSAVEC</a></td><td>Save Processor Extended States with Compaction</td><td></td></tr>
<tr><td><a href="./html/XSAVEOPT.html">XSAVEOPT</a></td><td>Save Processor Extended States Optimized</td><td>XSAVEOPT</td></tr>
<tr><td><a href="./html/XSAVES.html">XSAVES</a></td><td>Save Processor Extended States Supervisor</td><td></td></tr>
<tr><td><a href="./html/XSETBV.html">XSETBV</a></td><td>Set Extended Control Register</td><td></td></tr>
<tr><td><a href="./html/XTEST.html">XTEST</a></td><td>Test If In Transactional Execution</td><td>HLE, RTM</td></tr>
</table></body></html>